bugAVR C Runtime Library - Bugs: bug #28574, Xmega D ADC struct missing...


bug #28574: Xmega D ADC struct missing registers

Submitted by:  Eric Weddington <arcanum>
Submitted on:  Tue 12 Jan 2010 10:33:21 PM UTC  
Category:  Header Severity:  3 - Normal
Priority:  9 - Immediate Item Group:  None
Status:  Fixed Assigned to:  Anitha Boyapati <aboyapati>
Percent Complete:  100% Open/Closed:  Closed
Release:  1.6.7 Fixed Release:  None

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  Spam posted by susancai
Thu 15 Apr 2010 04:08:10 PM UTC, comment #11: 

Proper patch with Changelog and News entries generated for revision 2121. Build verified.

(file #20229)

Anitha Boyapati <aboyapati>In charge of this item.
Thu 15 Apr 2010 01:58:39 PM UTC, comment #10: 

As these reserved locations are part of a C struct, you
cannot have "holes" in them, so the C struct definition must
necessarily differ from the XML description (which can simply
omit the unused IO registers).

Filling these holes with "reserved_0x**" is already done in
other parts of the Xmega header files.  (I would probably
have preferred using __reserved_0x** so the names are in
the implementation namespace rather than the application
namespace, but that's already a little late right now.)

Joerg Wunsch <joerg_wunsch>
Project Administrator
Thu 15 Apr 2010 12:24:54 PM UTC, comment #9: 

I have reviewed Oliver's patch. The modifications in the patch match are compared with corresponding xml files.

1. Changes for ADC_T match xml device files. They appear fine.
2. Changes for EVSYS donot match xml device files. For e.g., the patch introduces new registers from 0x04-0x07 and 0x0C-0x0F which is not specified in ATxmega128d3.xml or ATxmega64D3.xml.

     register8_t CH2MUX;  /* Event Channel 2 Multiplexer */
     register8_t CH3MUX;  /* Event Channel 3 Multiplexer */
+    register8_t reserved_0x04;
+    register8_t reserved_0x05;
+    register8_t reserved_0x06;
+    register8_t reserved_0x07;
     register8_t CH0CTRL;  /* Channel 0 Control Register */
     register8_t CH1CTRL;  /* Channel 1 Control Register */
     register8_t CH2CTRL;  /* Channel 2 Control Register */
     register8_t CH3CTRL;  /* Channel 3 Control Register */
+    register8_t reserved_0x0C;
+    register8_t reserved_0x0D;
+    register8_t reserved_0x0E;
+    register8_t reserved_0x0F;
     register8_t STROBE;  /* Event Strobe */

I am not sure how if second change can be introduced without change xml device files. Can this bug deal with xml changes also?

Anitha Boyapati <aboyapati>In charge of this item.
Tue 13 Apr 2010 05:14:57 AM UTC, comment #8: 

Is there anything preventing the application of Oliver's patch?  From looking at the ATxmega16D4.xml file that is supplied with AVR Studio 4.18 Build 692, it appears that the xml file is correct, at least for the xmega16d4.


Galen Seitz <galens>
Wed 07 Apr 2010 04:16:32 AM UTC, comment #7: 


Our policy is to have the header files conform to the data in the XML device files that ship with AVR Studio. So please refer to those files for definitive answers.


Eric Weddington <arcanum>
Project Administrator
Tue 06 Apr 2010 07:42:11 AM UTC, comment #6: 

1. I am referring to doc8135.pdf from atmel website (XMEGA D4 preliminary). ADC overview (section 23) says, ADC has one channel only. Where exactly/else can we find out that XMEGA D4 has 4 ADC channels similar to that of XMEGA A4?

2. Assuming that D4 is similar to that of A4 in ADC structure and channels, I find that 2 more modifications are necessary other than the proposed 0x12-0x17 changes to ADC_t structure.

Firstly, 0x07 appears to be specified as TEMP register in A4 datasheet while it is termed as reserved in ALL xmega headers (just not limited to D4).

    register8_t reserved_0x07;

Secondly, offsets are required for other channels (1,2,3).
ADC_CH_t CH1;  /* ADC Channel 1 */
ADC_CH_t CH2;  /* ADC Channel 2 */
ADC_CH_t CH3;  /* ADC Channel 3 */

Anitha Boyapati <aboyapati>In charge of this item.
Tue 02 Feb 2010 03:14:23 PM UTC, comment #5: 

Thank you Eric for your prompt reply. I just received a manual for the D4 from the Danish FAE and it confirms that the D4 has just one ADC channel as opposed to four channels on the A4. The XML file of the latest AVR studio also defines just the one channel, like you hinted. I guess the datasheet will be revised in the near future.

Aksel Jensen <akseljensen>
Tue 02 Feb 2010 02:23:27 PM UTC, comment #4: 

All header files are generated from the XML device file that is shipped with AVR Studio. Our policy is to match the XML device file, not necessarily the data sheet.

If the header file and the data sheet are inconsistent, then you must look in the XML device file to see what it has. If the header file and the XML device file is inconsistent, then it is an avr-libc bug. If the data sheet and the XML device file are inconsistent, then you need to send an email to Atmel (avr AT atmel DOT com).

Eric Weddington <arcanum>
Project Administrator
Tue 02 Feb 2010 12:28:08 PM UTC, comment #3: 

The D4 datasheet (doc8135.pdf), indicates that the ADC on the D4 has 4 channels just as the A4.

I suspect that the ADC structure for the D4 should be more like the one for the A4. Am I correct?

The datasheet also indicates that the event system on the D4 has only 4 event channels, but the header file for the D4 refers to channels 4-7, at least as far as ADC event channel input selection goes.

Can anybody clarify?

I have not got a manual for D4 (it is probably not public yet).

Aksel Jensen <akseljensen>
Thu 14 Jan 2010 04:47:38 PM UTC, comment #2: 

The same problem exists on Xmega D with Event System registers
where EVSYS_t struct also misses blank registers.

I've attached a patch (file #19491) which applies against
avr-libc from cvs (01/10/2010 09:00). It fixes the ADC and
EVSYS issue for atxmega64d3, atxmega128d3, atxmega192d3,
atxmega256d3, atxmega16d4 and atxmega32d4

Olivier Gay <OUAH>
Tue 12 Jan 2010 10:34:46 PM UTC, comment #1: 

See the WinAVR bug report for any attached files.

Eric Weddington <arcanum>
Project Administrator
Tue 12 Jan 2010 10:33:21 PM UTC, original submission:  

From WinAVR bug #2889660 (SourceForge):

In the header files for the Xmega D series, the ADC_t struct is missing
several blank registers, resulting in the improper offset being calculated
when trying to access items further down the list. Specifically, offsets
0x12 - 0x17 or the spots occupied by the word registers for channels 1, 2,
and 3 in the Xmega A series. I have attached a fixed version for the 32D4

Eric Weddington <arcanum>
Project Administrator


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Attach Files:

Attached Files
file #20229:  bug28574.patch added by aboyapati (9KiB - application/octet-stream - Please review)


Depends on the following items: None found

Items that depend on this one: None found


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  • -email is unavailable- added by susancai (Posted a comment)
  • -email is unavailable- added by joerg_wunsch (Posted a comment)
  • -email is unavailable- added by galens (Posted a comment)
  • -email is unavailable- added by aboyapati (Posted a comment)
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  • -email is unavailable- added by OUAH (Updated the item)
  • -email is unavailable- added by arcanum (Submitted the item)



    Follow 8 latest changes.

    Date Changed by Updated Field Previous Value => Replaced by
    2010-06-10 aboyapati Open/ClosedOpen => Closed
    2010-04-16 aboyapati StatusIn Progress => Fixed
        Percent Complete0% => 100%
    2010-04-15 aboyapati Attached File- => Added bug28574.patch, #20229
    2010-04-06 aboyapati StatusNone => In Progress
        Assigned toNone => aboyapati
    2010-03-29 arcanum Priority5 - Normal => 9 - Immediate
    2010-01-14 OUAH Attached File- => Added avr-libc-cvs-100110-wrong-offset.patch, #19491

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