/[avr-libc]/avr-libc/include/avr/io4414.h
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Contents of /avr-libc/include/avr/io4414.h

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Revision 1.5 - (show annotations) (download)
Mon Nov 1 21:19:54 2004 UTC (19 years, 6 months ago) by arcanum
Branch: MAIN
CVS Tags: avr-libc-1_2_1-release, avr-libc-1_2_3-release, avr-libc-1_2_0-release, avr-libc-1_2_2-release, avr-libc-1_2-branchpoint
Branch point for: avr-libc-1_2-branch
Changes since 1.4: +6 -1 lines
File MIME type: text/plain
	* crt1/gcrt1.S: Correct license with permission from Marek
	Michalkiewicz.
	* common/macros.inc: Ditto.
	* include/errno.h: Ditto.
	* include/setjmp.h: Ditto.
	* include/stdint.h: Ditto.
	* include/string.h: Ditto.
	* include/avr/crc16.h: Ditto.
	* include/avr/delay.h: Ditto.
	* include/avr/eeprom.h: Ditto.
	* include/avr/interrupt.h: Ditto.
	* include/avr/io1200.h: Ditto.
	* include/avr/io2313.h: Ditto.
	* include/avr/io2323.h: Ditto.
	* include/avr/io2333.h: Ditto.
	* include/avr/io2343.h: Ditto.
	* include/avr/io4414.h: Ditto.
	* include/avr/io4433.h: Ditto.
	* include/avr/io4434.h: Ditto.
	* include/avr/io76c711.h: Ditto.
	* include/avr/sfr_defs.h: Ditto.
	* include/avr/signal.h: Ditto.
	* include/avr/twi.h: Ditto.

1 /* Copyright (c) 2002, Marek Michalkiewicz
2 All rights reserved.
3
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions are met:
6
7 * Redistributions of source code must retain the above copyright
8 notice, this list of conditions and the following disclaimer.
9
10 * Redistributions in binary form must reproduce the above copyright
11 notice, this list of conditions and the following disclaimer in
12 the documentation and/or other materials provided with the
13 distribution.
14
15 * Neither the name of the copyright holders nor the names of
16 contributors may be used to endorse or promote products derived
17 from this software without specific prior written permission.
18
19 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 POSSIBILITY OF SUCH DAMAGE. */
30
31 /* $Id: io4414.h,v 1.4 2003/01/08 11:14:10 joerg_wunsch Exp $ */
32
33 /* avr/io4414.h - definitions for AT90S4414 */
34
35 #ifndef _AVR_IO4414_H_
36 #define _AVR_IO4414_H_ 1
37
38 /* This file should only be included from <avr/io.h>, never directly. */
39
40 #ifndef _AVR_IO_H_
41 # error "Include <avr/io.h> instead of this file."
42 #endif
43
44 #ifndef _AVR_IOXXX_H_
45 # define _AVR_IOXXX_H_ "io4414.h"
46 #else
47 # error "Attempt to include more than one <avr/ioXXX.h> file."
48 #endif
49
50 /* I/O registers */
51
52 /* Analog Comparator Control and Status Register */
53 #define ACSR _SFR_IO8(0x08)
54
55 /* UART Baud Rate Register */
56 #define UBRR _SFR_IO8(0x09)
57
58 /* UART Control Register */
59 #define UCR _SFR_IO8(0x0A)
60
61 /* UART Status Register */
62 #define USR _SFR_IO8(0x0B)
63
64 /* UART I/O Data Register */
65 #define UDR _SFR_IO8(0x0C)
66
67 /* SPI Control Register */
68 #define SPCR _SFR_IO8(0x0D)
69
70 /* SPI Status Register */
71 #define SPSR _SFR_IO8(0x0E)
72
73 /* SPI I/O Data Register */
74 #define SPDR _SFR_IO8(0x0F)
75
76 /* Input Pins, Port D */
77 #define PIND _SFR_IO8(0x10)
78
79 /* Data Direction Register, Port D */
80 #define DDRD _SFR_IO8(0x11)
81
82 /* Data Register, Port D */
83 #define PORTD _SFR_IO8(0x12)
84
85 /* Input Pins, Port C */
86 #define PINC _SFR_IO8(0x13)
87
88 /* Data Direction Register, Port C */
89 #define DDRC _SFR_IO8(0x14)
90
91 /* Data Register, Port C */
92 #define PORTC _SFR_IO8(0x15)
93
94 /* Input Pins, Port B */
95 #define PINB _SFR_IO8(0x16)
96
97 /* Data Direction Register, Port B */
98 #define DDRB _SFR_IO8(0x17)
99
100 /* Data Register, Port B */
101 #define PORTB _SFR_IO8(0x18)
102
103 /* Input Pins, Port A */
104 #define PINA _SFR_IO8(0x19)
105
106 /* Data Direction Register, Port A */
107 #define DDRA _SFR_IO8(0x1A)
108
109 /* Data Register, Port A */
110 #define PORTA _SFR_IO8(0x1B)
111
112 /* 0x1C..0x1F EEPROM */
113
114 /* Watchdog Timer Control Register */
115 #define WDTCR _SFR_IO8(0x21)
116
117 /* T/C 1 Input Capture Register */
118 #define ICR1 _SFR_IO16(0x24)
119 #define ICR1L _SFR_IO8(0x24)
120 #define ICR1H _SFR_IO8(0x25)
121
122 /* Timer/Counter1 Output Compare Register B */
123 #define OCR1B _SFR_IO16(0x28)
124 #define OCR1BL _SFR_IO8(0x28)
125 #define OCR1BH _SFR_IO8(0x29)
126
127 /* Timer/Counter1 Output Compare Register A */
128 #define OCR1A _SFR_IO16(0x2A)
129 #define OCR1AL _SFR_IO8(0x2A)
130 #define OCR1AH _SFR_IO8(0x2B)
131
132 /* Timer/Counter 1 */
133 #define TCNT1 _SFR_IO16(0x2C)
134 #define TCNT1L _SFR_IO8(0x2C)
135 #define TCNT1H _SFR_IO8(0x2D)
136
137 /* Timer/Counter 1 Control and Status Register */
138 #define TCCR1B _SFR_IO8(0x2E)
139
140 /* Timer/Counter 1 Control Register */
141 #define TCCR1A _SFR_IO8(0x2F)
142
143 /* Timer/Counter 0 */
144 #define TCNT0 _SFR_IO8(0x32)
145
146 /* Timer/Counter 0 Control Register */
147 #define TCCR0 _SFR_IO8(0x33)
148
149 /* MCU general Control Register */
150 #define MCUCR _SFR_IO8(0x35)
151
152 /* Timer/Counter Interrupt Flag register */
153 #define TIFR _SFR_IO8(0x38)
154
155 /* Timer/Counter Interrupt MaSK register */
156 #define TIMSK _SFR_IO8(0x39)
157
158 /* General Interrupt Flag Register */
159 #define GIFR _SFR_IO8(0x3A)
160
161 /* General Interrupt MaSK register */
162 #define GIMSK _SFR_IO8(0x3B)
163
164 /* 0x3C..0x3D SP */
165
166 /* 0x3F SREG */
167
168 /* Interrupt vectors */
169
170 #define SIG_INTERRUPT0 _VECTOR(1)
171 #define SIG_INTERRUPT1 _VECTOR(2)
172 #define SIG_INPUT_CAPTURE1 _VECTOR(3)
173 #define SIG_OUTPUT_COMPARE1A _VECTOR(4)
174 #define SIG_OUTPUT_COMPARE1B _VECTOR(5)
175 #define SIG_OVERFLOW1 _VECTOR(6)
176 #define SIG_OVERFLOW0 _VECTOR(7)
177 #define SIG_SPI _VECTOR(8)
178 #define SIG_UART_RECV _VECTOR(9)
179 #define SIG_UART_DATA _VECTOR(10)
180 #define SIG_UART_TRANS _VECTOR(11)
181 #define SIG_COMPARATOR _VECTOR(12)
182
183 #define _VECTORS_SIZE 26
184
185 /*
186 The Register Bit names are represented by their bit number (0-7).
187 */
188
189 /* General Interrupt MaSK register */
190 #define INT1 7
191 #define INT0 6
192
193 /* General Interrupt Flag Register */
194 #define INTF1 7
195 #define INTF0 6
196
197 /* Timer/Counter Interrupt MaSK register */
198 #define TOIE1 7
199 #define OCIE1A 6
200 #define OCIE1B 5
201 #define TICIE1 3
202 #define TOIE0 1
203
204 /* Timer/Counter Interrupt Flag register */
205 #define TOV1 7
206 #define OCF1A 6
207 #define OCF1B 5
208 #define ICF1 3
209 #define TOV0 1
210
211 /* MCU general Control Register */
212 #define SRE 7
213 #define SRW 6
214 #define SE 5
215 #define SM 4
216 #define ISC11 3
217 #define ISC10 2
218 #define ISC01 1
219 #define ISC00 0
220
221 /* Timer/Counter 0 Control Register */
222 #define CS02 2
223 #define CS01 1
224 #define CS00 0
225
226 /* Timer/Counter 1 Control Register */
227 #define COM1A1 7
228 #define COM1A0 6
229 #define COM1B1 5
230 #define COM1B0 4
231 #define PWM11 1
232 #define PWM10 0
233
234 /* Timer/Counter 1 Control and Status Register */
235 #define ICNC1 7
236 #define ICES1 6
237 #define CTC1 3
238 #define CS12 2
239 #define CS11 1
240 #define CS10 0
241
242 /* Watchdog Timer Control Register */
243 #define WDTOE 4
244 #define WDE 3
245 #define WDP2 2
246 #define WDP1 1
247 #define WDP0 0
248
249 /* Data Register, Port A */
250 #define PA7 7
251 #define PA6 6
252 #define PA5 5
253 #define PA4 4
254 #define PA3 3
255 #define PA2 2
256 #define PA1 1
257 #define PA0 0
258
259 /* Data Direction Register, Port A */
260 #define DDA7 7
261 #define DDA6 6
262 #define DDA5 5
263 #define DDA4 4
264 #define DDA3 3
265 #define DDA2 2
266 #define DDA1 1
267 #define DDA0 0
268
269 /* Input Pins, Port A */
270 #define PINA7 7
271 #define PINA6 6
272 #define PINA5 5
273 #define PINA4 4
274 #define PINA3 3
275 #define PINA2 2
276 #define PINA1 1
277 #define PINA0 0
278
279 /* Data Register, Port B */
280 #define PB7 7
281 #define PB6 6
282 #define PB5 5
283 #define PB4 4
284 #define PB3 3
285 #define PB2 2
286 #define PB1 1
287 #define PB0 0
288
289 /* Data Direction Register, Port B */
290 #define DDB7 7
291 #define DDB6 6
292 #define DDB5 5
293 #define DDB4 4
294 #define DDB3 3
295 #define DDB2 2
296 #define DDB1 1
297 #define DDB0 0
298
299 /* Input Pins, Port B */
300 #define PINB7 7
301 #define PINB6 6
302 #define PINB5 5
303 #define PINB4 4
304 #define PINB3 3
305 #define PINB2 2
306 #define PINB1 1
307 #define PINB0 0
308
309 /* Data Register, Port C */
310 #define PC7 7
311 #define PC6 6
312 #define PC5 5
313 #define PC4 4
314 #define PC3 3
315 #define PC2 2
316 #define PC1 1
317 #define PC0 0
318
319 /* Data Direction Register, Port C */
320 #define DDC7 7
321 #define DDC6 6
322 #define DDC5 5
323 #define DDC4 4
324 #define DDC3 3
325 #define DDC2 2
326 #define DDC1 1
327 #define DDC0 0
328
329 /* Input Pins, Port C */
330 #define PINC7 7
331 #define PINC6 6
332 #define PINC5 5
333 #define PINC4 4
334 #define PINC3 3
335 #define PINC2 2
336 #define PINC1 1
337 #define PINC0 0
338
339 /* Data Register, Port D */
340 #define PD7 7
341 #define PD6 6
342 #define PD5 5
343 #define PD4 4
344 #define PD3 3
345 #define PD2 2
346 #define PD1 1
347 #define PD0 0
348
349 /* Data Direction Register, Port D */
350 #define DDD7 7
351 #define DDD6 6
352 #define DDD5 5
353 #define DDD4 4
354 #define DDD3 3
355 #define DDD2 2
356 #define DDD1 1
357 #define DDD0 0
358
359 /* Input Pins, Port D */
360 #define PIND7 7
361 #define PIND6 6
362 #define PIND5 5
363 #define PIND4 4
364 #define PIND3 3
365 #define PIND2 2
366 #define PIND1 1
367 #define PIND0 0
368
369 /* SPI Status Register */
370 #define SPIF 7
371 #define WCOL 6
372
373 /* SPI Control Register */
374 #define SPIE 7
375 #define SPE 6
376 #define DORD 5
377 #define MSTR 4
378 #define CPOL 3
379 #define CPHA 2
380 #define SPR1 1
381 #define SPR0 0
382
383 /* UART Status Register */
384 #define RXC 7
385 #define TXC 6
386 #define UDRE 5
387 #define FE 4
388 #define DOR 3
389
390 /* UART Control Register */
391 #define RXCIE 7
392 #define TXCIE 6
393 #define UDRIE 5
394 #define RXEN 4
395 #define TXEN 3
396 #define CHR9 2
397 #define RXB8 1
398 #define TXB8 0
399
400 /* Analog Comparator Control and Status Register */
401 #define ACD 7
402 #define ACO 5
403 #define ACI 4
404 #define ACIE 3
405 #define ACIC 2
406 #define ACIS1 1
407 #define ACIS0 0
408
409 /* Constants */
410 #define RAMEND 0x15F /* Last On-Chip SRAM Location */
411 #define XRAMEND 0xFFFF
412 #define E2END 0xFF
413 #define FLASHEND 0xFFF
414
415 #endif /* _AVR_IO4414_H_ */

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