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/* Copyright (c) 2002, Marek Michalkiewicz |
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All rights reserved. |
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|
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Redistribution and use in source and binary forms, with or without |
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modification, are permitted provided that the following conditions are met: |
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|
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* Redistributions of source code must retain the above copyright |
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notice, this list of conditions and the following disclaimer. |
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|
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* Redistributions in binary form must reproduce the above copyright |
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notice, this list of conditions and the following disclaimer in |
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the documentation and/or other materials provided with the |
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distribution. |
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|
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* Neither the name of the copyright holders nor the names of |
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contributors may be used to endorse or promote products derived |
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from this software without specific prior written permission. |
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|
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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POSSIBILITY OF SUCH DAMAGE. */ |
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|
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/* $Id: io4414.h,v 1.4 2003/01/08 11:14:10 joerg_wunsch Exp $ */ |
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|
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/* avr/io4414.h - definitions for AT90S4414 */ |
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|
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#ifndef _AVR_IO4414_H_ |
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#define _AVR_IO4414_H_ 1 |
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|
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/* This file should only be included from <avr/io.h>, never directly. */ |
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|
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#ifndef _AVR_IO_H_ |
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# error "Include <avr/io.h> instead of this file." |
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#endif |
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|
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#ifndef _AVR_IOXXX_H_ |
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# define _AVR_IOXXX_H_ "io4414.h" |
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#else |
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# error "Attempt to include more than one <avr/ioXXX.h> file." |
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#endif |
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|
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/* I/O registers */ |
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|
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/* Analog Comparator Control and Status Register */ |
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#define ACSR _SFR_IO8(0x08) |
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|
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/* UART Baud Rate Register */ |
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#define UBRR _SFR_IO8(0x09) |
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|
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/* UART Control Register */ |
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#define UCR _SFR_IO8(0x0A) |
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|
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/* UART Status Register */ |
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#define USR _SFR_IO8(0x0B) |
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|
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/* UART I/O Data Register */ |
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#define UDR _SFR_IO8(0x0C) |
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|
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/* SPI Control Register */ |
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#define SPCR _SFR_IO8(0x0D) |
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|
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/* SPI Status Register */ |
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#define SPSR _SFR_IO8(0x0E) |
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|
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/* SPI I/O Data Register */ |
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#define SPDR _SFR_IO8(0x0F) |
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|
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/* Input Pins, Port D */ |
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#define PIND _SFR_IO8(0x10) |
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|
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/* Data Direction Register, Port D */ |
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#define DDRD _SFR_IO8(0x11) |
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|
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/* Data Register, Port D */ |
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#define PORTD _SFR_IO8(0x12) |
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|
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/* Input Pins, Port C */ |
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#define PINC _SFR_IO8(0x13) |
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|
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/* Data Direction Register, Port C */ |
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#define DDRC _SFR_IO8(0x14) |
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|
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/* Data Register, Port C */ |
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#define PORTC _SFR_IO8(0x15) |
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|
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/* Input Pins, Port B */ |
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#define PINB _SFR_IO8(0x16) |
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|
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/* Data Direction Register, Port B */ |
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#define DDRB _SFR_IO8(0x17) |
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|
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/* Data Register, Port B */ |
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#define PORTB _SFR_IO8(0x18) |
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|
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/* Input Pins, Port A */ |
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#define PINA _SFR_IO8(0x19) |
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|
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/* Data Direction Register, Port A */ |
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#define DDRA _SFR_IO8(0x1A) |
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|
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/* Data Register, Port A */ |
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#define PORTA _SFR_IO8(0x1B) |
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|
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/* 0x1C..0x1F EEPROM */ |
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|
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/* Watchdog Timer Control Register */ |
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#define WDTCR _SFR_IO8(0x21) |
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|
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/* T/C 1 Input Capture Register */ |
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#define ICR1 _SFR_IO16(0x24) |
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#define ICR1L _SFR_IO8(0x24) |
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#define ICR1H _SFR_IO8(0x25) |
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|
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/* Timer/Counter1 Output Compare Register B */ |
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#define OCR1B _SFR_IO16(0x28) |
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#define OCR1BL _SFR_IO8(0x28) |
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#define OCR1BH _SFR_IO8(0x29) |
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|
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/* Timer/Counter1 Output Compare Register A */ |
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#define OCR1A _SFR_IO16(0x2A) |
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#define OCR1AL _SFR_IO8(0x2A) |
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#define OCR1AH _SFR_IO8(0x2B) |
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|
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/* Timer/Counter 1 */ |
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#define TCNT1 _SFR_IO16(0x2C) |
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#define TCNT1L _SFR_IO8(0x2C) |
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#define TCNT1H _SFR_IO8(0x2D) |
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|
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/* Timer/Counter 1 Control and Status Register */ |
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#define TCCR1B _SFR_IO8(0x2E) |
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|
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/* Timer/Counter 1 Control Register */ |
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#define TCCR1A _SFR_IO8(0x2F) |
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|
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/* Timer/Counter 0 */ |
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#define TCNT0 _SFR_IO8(0x32) |
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|
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/* Timer/Counter 0 Control Register */ |
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#define TCCR0 _SFR_IO8(0x33) |
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|
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/* MCU general Control Register */ |
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#define MCUCR _SFR_IO8(0x35) |
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|
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/* Timer/Counter Interrupt Flag register */ |
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#define TIFR _SFR_IO8(0x38) |
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|
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/* Timer/Counter Interrupt MaSK register */ |
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#define TIMSK _SFR_IO8(0x39) |
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|
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/* General Interrupt Flag Register */ |
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#define GIFR _SFR_IO8(0x3A) |
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|
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/* General Interrupt MaSK register */ |
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#define GIMSK _SFR_IO8(0x3B) |
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|
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/* 0x3C..0x3D SP */ |
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|
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/* 0x3F SREG */ |
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|
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/* Interrupt vectors */ |
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|
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#define SIG_INTERRUPT0 _VECTOR(1) |
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#define SIG_INTERRUPT1 _VECTOR(2) |
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#define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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#define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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#define SIG_OUTPUT_COMPARE1B _VECTOR(5) |
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#define SIG_OVERFLOW1 _VECTOR(6) |
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#define SIG_OVERFLOW0 _VECTOR(7) |
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#define SIG_SPI _VECTOR(8) |
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#define SIG_UART_RECV _VECTOR(9) |
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#define SIG_UART_DATA _VECTOR(10) |
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#define SIG_UART_TRANS _VECTOR(11) |
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#define SIG_COMPARATOR _VECTOR(12) |
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|
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#define _VECTORS_SIZE 26 |
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|
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/* |
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The Register Bit names are represented by their bit number (0-7). |
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*/ |
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|
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/* General Interrupt MaSK register */ |
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#define INT1 7 |
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#define INT0 6 |
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|
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/* General Interrupt Flag Register */ |
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#define INTF1 7 |
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#define INTF0 6 |
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|
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/* Timer/Counter Interrupt MaSK register */ |
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#define TOIE1 7 |
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#define OCIE1A 6 |
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#define OCIE1B 5 |
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#define TICIE1 3 |
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#define TOIE0 1 |
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|
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/* Timer/Counter Interrupt Flag register */ |
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#define TOV1 7 |
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#define OCF1A 6 |
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#define OCF1B 5 |
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#define ICF1 3 |
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#define TOV0 1 |
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|
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/* MCU general Control Register */ |
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#define SRE 7 |
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#define SRW 6 |
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#define SE 5 |
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#define SM 4 |
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#define ISC11 3 |
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#define ISC10 2 |
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#define ISC01 1 |
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#define ISC00 0 |
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|
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/* Timer/Counter 0 Control Register */ |
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#define CS02 2 |
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#define CS01 1 |
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#define CS00 0 |
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|
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/* Timer/Counter 1 Control Register */ |
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#define COM1A1 7 |
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#define COM1A0 6 |
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#define COM1B1 5 |
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#define COM1B0 4 |
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#define PWM11 1 |
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#define PWM10 0 |
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|
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/* Timer/Counter 1 Control and Status Register */ |
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#define ICNC1 7 |
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#define ICES1 6 |
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#define CTC1 3 |
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#define CS12 2 |
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#define CS11 1 |
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#define CS10 0 |
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|
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/* Watchdog Timer Control Register */ |
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#define WDTOE 4 |
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#define WDE 3 |
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#define WDP2 2 |
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#define WDP1 1 |
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#define WDP0 0 |
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|
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/* Data Register, Port A */ |
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#define PA7 7 |
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#define PA6 6 |
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#define PA5 5 |
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#define PA4 4 |
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#define PA3 3 |
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#define PA2 2 |
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#define PA1 1 |
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#define PA0 0 |
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|
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/* Data Direction Register, Port A */ |
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#define DDA7 7 |
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#define DDA6 6 |
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#define DDA5 5 |
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#define DDA4 4 |
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#define DDA3 3 |
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#define DDA2 2 |
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#define DDA1 1 |
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#define DDA0 0 |
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|
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/* Input Pins, Port A */ |
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#define PINA7 7 |
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#define PINA6 6 |
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#define PINA5 5 |
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#define PINA4 4 |
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#define PINA3 3 |
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#define PINA2 2 |
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#define PINA1 1 |
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#define PINA0 0 |
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|
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/* Data Register, Port B */ |
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#define PB7 7 |
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#define PB6 6 |
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#define PB5 5 |
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#define PB4 4 |
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#define PB3 3 |
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#define PB2 2 |
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#define PB1 1 |
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#define PB0 0 |
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|
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/* Data Direction Register, Port B */ |
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#define DDB7 7 |
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#define DDB6 6 |
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#define DDB5 5 |
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#define DDB4 4 |
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#define DDB3 3 |
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#define DDB2 2 |
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#define DDB1 1 |
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#define DDB0 0 |
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|
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/* Input Pins, Port B */ |
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#define PINB7 7 |
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#define PINB6 6 |
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#define PINB5 5 |
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#define PINB4 4 |
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#define PINB3 3 |
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#define PINB2 2 |
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#define PINB1 1 |
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#define PINB0 0 |
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|
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/* Data Register, Port C */ |
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#define PC7 7 |
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#define PC6 6 |
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#define PC5 5 |
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#define PC4 4 |
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#define PC3 3 |
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#define PC2 2 |
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#define PC1 1 |
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#define PC0 0 |
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|
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/* Data Direction Register, Port C */ |
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#define DDC7 7 |
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#define DDC6 6 |
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#define DDC5 5 |
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#define DDC4 4 |
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#define DDC3 3 |
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#define DDC2 2 |
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#define DDC1 1 |
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#define DDC0 0 |
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|
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/* Input Pins, Port C */ |
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#define PINC7 7 |
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#define PINC6 6 |
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#define PINC5 5 |
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#define PINC4 4 |
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#define PINC3 3 |
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#define PINC2 2 |
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#define PINC1 1 |
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#define PINC0 0 |
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|
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/* Data Register, Port D */ |
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#define PD7 7 |
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#define PD6 6 |
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#define PD5 5 |
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#define PD4 4 |
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#define PD3 3 |
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#define PD2 2 |
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#define PD1 1 |
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#define PD0 0 |
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|
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/* Data Direction Register, Port D */ |
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#define DDD7 7 |
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#define DDD6 6 |
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#define DDD5 5 |
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#define DDD4 4 |
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#define DDD3 3 |
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#define DDD2 2 |
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#define DDD1 1 |
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#define DDD0 0 |
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|
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/* Input Pins, Port D */ |
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#define PIND7 7 |
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#define PIND6 6 |
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#define PIND5 5 |
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#define PIND4 4 |
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#define PIND3 3 |
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#define PIND2 2 |
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#define PIND1 1 |
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#define PIND0 0 |
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|
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/* SPI Status Register */ |
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#define SPIF 7 |
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#define WCOL 6 |
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|
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/* SPI Control Register */ |
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#define SPIE 7 |
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#define SPE 6 |
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#define DORD 5 |
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#define MSTR 4 |
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#define CPOL 3 |
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#define CPHA 2 |
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#define SPR1 1 |
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#define SPR0 0 |
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|
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/* UART Status Register */ |
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#define RXC 7 |
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#define TXC 6 |
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#define UDRE 5 |
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#define FE 4 |
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#define DOR 3 |
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|
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/* UART Control Register */ |
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#define RXCIE 7 |
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#define TXCIE 6 |
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#define UDRIE 5 |
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#define RXEN 4 |
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#define TXEN 3 |
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#define CHR9 2 |
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#define RXB8 1 |
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#define TXB8 0 |
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|
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/* Analog Comparator Control and Status Register */ |
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#define ACD 7 |
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#define ACO 5 |
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#define ACI 4 |
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#define ACIE 3 |
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#define ACIC 2 |
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#define ACIS1 1 |
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#define ACIS0 0 |
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|
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/* Constants */ |
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#define RAMEND 0x15F /* Last On-Chip SRAM Location */ |
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#define XRAMEND 0xFFFF |
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#define E2END 0xFF |
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#define FLASHEND 0xFFF |
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|
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#endif /* _AVR_IO4414_H_ */ |