1 |
/* Copyright (c) 2002, Peter Jansen |
2 |
All rights reserved. |
3 |
|
4 |
Redistribution and use in source and binary forms, with or without |
5 |
modification, are permitted provided that the following conditions are met: |
6 |
|
7 |
* Redistributions of source code must retain the above copyright |
8 |
notice, this list of conditions and the following disclaimer. |
9 |
* Redistributions in binary form must reproduce the above copyright |
10 |
notice, this list of conditions and the following disclaimer in |
11 |
the documentation and/or other materials provided with the |
12 |
distribution. |
13 |
|
14 |
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
15 |
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
16 |
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
17 |
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
18 |
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
19 |
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
20 |
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
21 |
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
22 |
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
23 |
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
24 |
POSSIBILITY OF SUCH DAMAGE. */ |
25 |
|
26 |
/* avr/iom128.h - defines for ATmega128 |
27 |
|
28 |
As of 2002-08-27: |
29 |
- This should be up to date with data sheet 2467E-AVR-05/02 */ |
30 |
|
31 |
#ifndef _AVR_IOM128_H_ |
32 |
#define _AVR_IOM128_H_ 1 |
33 |
|
34 |
/* This file should only be included from <avr/io.h>, never directly. */ |
35 |
|
36 |
#ifndef _AVR_IO_H_ |
37 |
# error "Include <avr/io.h> instead of this file." |
38 |
#endif |
39 |
|
40 |
#ifndef _AVR_IOXXX_H_ |
41 |
# define _AVR_IOXXX_H_ "iom128.h" |
42 |
#else |
43 |
# error "Attempt to include more than one <avr/ioXXX.h> file." |
44 |
#endif |
45 |
|
46 |
#include <avr/sfr_defs.h> |
47 |
|
48 |
/* I/O registers */ |
49 |
|
50 |
/* Input Pins, Port F */ |
51 |
#define PINF _SFR_IO8(0x00) |
52 |
|
53 |
/* Input Pins, Port E */ |
54 |
#define PINE _SFR_IO8(0x01) |
55 |
|
56 |
/* Data Direction Register, Port E */ |
57 |
#define DDRE _SFR_IO8(0x02) |
58 |
|
59 |
/* Data Register, Port E */ |
60 |
#define PORTE _SFR_IO8(0x03) |
61 |
|
62 |
/* ADC Data Register */ |
63 |
#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ |
64 |
#define ADC _SFR_IO16(0x04) |
65 |
#define ADCL _SFR_IO8(0x04) |
66 |
#define ADCH _SFR_IO8(0x05) |
67 |
|
68 |
/* ADC Control and status register */ |
69 |
#define ADCSR _SFR_IO8(0x06) |
70 |
#define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ |
71 |
|
72 |
/* ADC Multiplexer select */ |
73 |
#define ADMUX _SFR_IO8(0x07) |
74 |
|
75 |
/* Analog Comparator Control and Status Register */ |
76 |
#define ACSR _SFR_IO8(0x08) |
77 |
|
78 |
/* USART0 Baud Rate Register Low */ |
79 |
#define UBRR0L _SFR_IO8(0x09) |
80 |
|
81 |
/* USART0 Control and Status Register B */ |
82 |
#define UCSR0B _SFR_IO8(0x0A) |
83 |
|
84 |
/* USART0 Control and Status Register A */ |
85 |
#define UCSR0A _SFR_IO8(0x0B) |
86 |
|
87 |
/* USART0 I/O Data Register */ |
88 |
#define UDR0 _SFR_IO8(0x0C) |
89 |
|
90 |
/* SPI Control Register */ |
91 |
#define SPCR _SFR_IO8(0x0D) |
92 |
|
93 |
/* SPI Status Register */ |
94 |
#define SPSR _SFR_IO8(0x0E) |
95 |
|
96 |
/* SPI I/O Data Register */ |
97 |
#define SPDR _SFR_IO8(0x0F) |
98 |
|
99 |
/* Input Pins, Port D */ |
100 |
#define PIND _SFR_IO8(0x10) |
101 |
|
102 |
/* Data Direction Register, Port D */ |
103 |
#define DDRD _SFR_IO8(0x11) |
104 |
|
105 |
/* Data Register, Port D */ |
106 |
#define PORTD _SFR_IO8(0x12) |
107 |
|
108 |
/* Input Pins, Port C */ |
109 |
#define PINC _SFR_IO8(0x13) |
110 |
|
111 |
/* Data Direction Register, Port C */ |
112 |
#define DDRC _SFR_IO8(0x14) |
113 |
|
114 |
/* Data Register, Port C */ |
115 |
#define PORTC _SFR_IO8(0x15) |
116 |
|
117 |
/* Input Pins, Port B */ |
118 |
#define PINB _SFR_IO8(0x16) |
119 |
|
120 |
/* Data Direction Register, Port B */ |
121 |
#define DDRB _SFR_IO8(0x17) |
122 |
|
123 |
/* Data Register, Port B */ |
124 |
#define PORTB _SFR_IO8(0x18) |
125 |
|
126 |
/* Input Pins, Port A */ |
127 |
#define PINA _SFR_IO8(0x19) |
128 |
|
129 |
/* Data Direction Register, Port A */ |
130 |
#define DDRA _SFR_IO8(0x1A) |
131 |
|
132 |
/* Data Register, Port A */ |
133 |
#define PORTA _SFR_IO8(0x1B) |
134 |
|
135 |
/* EEPROM Control Register */ |
136 |
#define EECR _SFR_IO8(0x1C) |
137 |
|
138 |
/* EEPROM Data Register */ |
139 |
#define EEDR _SFR_IO8(0x1D) |
140 |
|
141 |
/* EEPROM Address Register */ |
142 |
#define EEAR _SFR_IO16(0x1E) |
143 |
#define EEARL _SFR_IO8(0x1E) |
144 |
#define EEARH _SFR_IO8(0x1F) |
145 |
|
146 |
/* Special Function I/O Register */ |
147 |
#define SFIOR _SFR_IO8(0x20) |
148 |
|
149 |
/* Watchdog Timer Control Register */ |
150 |
#define WDTCR _SFR_IO8(0x21) |
151 |
|
152 |
/* On-chip Debug Register */ |
153 |
#define OCDR _SFR_IO8(0x22) |
154 |
|
155 |
/* Timer2 Output Compare Register */ |
156 |
#define OCR2 _SFR_IO8(0x23) |
157 |
|
158 |
/* Timer/Counter 2 */ |
159 |
#define TCNT2 _SFR_IO8(0x24) |
160 |
|
161 |
/* Timer/Counter 2 Control register */ |
162 |
#define TCCR2 _SFR_IO8(0x25) |
163 |
|
164 |
/* T/C 1 Input Capture Register */ |
165 |
#define ICR1 _SFR_IO16(0x26) |
166 |
#define ICR1L _SFR_IO8(0x26) |
167 |
#define ICR1H _SFR_IO8(0x27) |
168 |
|
169 |
/* Timer/Counter1 Output Compare Register B */ |
170 |
#define OCR1B _SFR_IO16(0x28) |
171 |
#define OCR1BL _SFR_IO8(0x28) |
172 |
#define OCR1BH _SFR_IO8(0x29) |
173 |
|
174 |
/* Timer/Counter1 Output Compare Register A */ |
175 |
#define OCR1A _SFR_IO16(0x2A) |
176 |
#define OCR1AL _SFR_IO8(0x2A) |
177 |
#define OCR1AH _SFR_IO8(0x2B) |
178 |
|
179 |
/* Timer/Counter 1 */ |
180 |
#define TCNT1 _SFR_IO16(0x2C) |
181 |
#define TCNT1L _SFR_IO8(0x2C) |
182 |
#define TCNT1H _SFR_IO8(0x2D) |
183 |
|
184 |
/* Timer/Counter 1 Control and Status Register */ |
185 |
#define TCCR1B _SFR_IO8(0x2E) |
186 |
|
187 |
/* Timer/Counter 1 Control Register */ |
188 |
#define TCCR1A _SFR_IO8(0x2F) |
189 |
|
190 |
/* Timer/Counter 0 Asynchronous Control & Status Register */ |
191 |
#define ASSR _SFR_IO8(0x30) |
192 |
|
193 |
/* Output Compare Register 0 */ |
194 |
#define OCR0 _SFR_IO8(0x31) |
195 |
|
196 |
/* Timer/Counter 0 */ |
197 |
#define TCNT0 _SFR_IO8(0x32) |
198 |
|
199 |
/* Timer/Counter 0 Control Register */ |
200 |
#define TCCR0 _SFR_IO8(0x33) |
201 |
|
202 |
/* MCU Status Register */ |
203 |
#define MCUSR _SFR_IO8(0x34) |
204 |
#define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ |
205 |
|
206 |
/* MCU general Control Register */ |
207 |
#define MCUCR _SFR_IO8(0x35) |
208 |
|
209 |
/* Timer/Counter Interrupt Flag Register */ |
210 |
#define TIFR _SFR_IO8(0x36) |
211 |
|
212 |
/* Timer/Counter Interrupt MaSK register */ |
213 |
#define TIMSK _SFR_IO8(0x37) |
214 |
|
215 |
/* External Interrupt Flag Register */ |
216 |
#define EIFR _SFR_IO8(0x38) |
217 |
|
218 |
/* External Interrupt MaSK register */ |
219 |
#define EIMSK _SFR_IO8(0x39) |
220 |
|
221 |
/* External Interrupt Control Register B */ |
222 |
#define EICRB _SFR_IO8(0x3A) |
223 |
|
224 |
/* RAM Page Z select register */ |
225 |
#define RAMPZ _SFR_IO8(0x3B) |
226 |
|
227 |
/* XDIV Divide control register */ |
228 |
#define XDIV _SFR_IO8(0x3C) |
229 |
|
230 |
/* Stack Pointer */ |
231 |
#define SP _SFR_IO16(0x3D) |
232 |
#define SPL _SFR_IO8(0x3D) |
233 |
#define SPH _SFR_IO8(0x3E) |
234 |
|
235 |
/* Status REGister */ |
236 |
#define SREG _SFR_IO8(0x3F) |
237 |
|
238 |
/* Extended I/O registers */ |
239 |
|
240 |
/* Data Direction Register, Port F */ |
241 |
#define DDRF _SFR_MEM8(0x61) |
242 |
|
243 |
/* Data Register, Port F */ |
244 |
#define PORTF _SFR_MEM8(0x62) |
245 |
|
246 |
/* Input Pins, Port G */ |
247 |
#define PING _SFR_MEM8(0x63) |
248 |
|
249 |
/* Data Direction Register, Port G */ |
250 |
#define DDRG _SFR_MEM8(0x64) |
251 |
|
252 |
/* Data Register, Port G */ |
253 |
#define PORTG _SFR_MEM8(0x65) |
254 |
|
255 |
/* Store Program Memory Control and Status Register */ |
256 |
#define SPMCR _SFR_MEM8(0x68) |
257 |
#define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ |
258 |
|
259 |
/* External Interrupt Control Register A */ |
260 |
#define EICRA _SFR_MEM8(0x6A) |
261 |
|
262 |
/* External Memory Control Register B */ |
263 |
#define XMCRB _SFR_MEM8(0x6C) |
264 |
|
265 |
/* External Memory Control Register A */ |
266 |
#define XMCRA _SFR_MEM8(0x6D) |
267 |
|
268 |
/* Oscillator Calibration Register */ |
269 |
#define OSCCAL _SFR_MEM8(0x6F) |
270 |
|
271 |
/* 2-wire Serial Interface Bit Rate Register */ |
272 |
#define TWBR _SFR_MEM8(0x70) |
273 |
|
274 |
/* 2-wire Serial Interface Status Register */ |
275 |
#define TWSR _SFR_MEM8(0x71) |
276 |
|
277 |
/* 2-wire Serial Interface Address Register */ |
278 |
#define TWAR _SFR_MEM8(0x72) |
279 |
|
280 |
/* 2-wire Serial Interface Data Register */ |
281 |
#define TWDR _SFR_MEM8(0x73) |
282 |
|
283 |
/* 2-wire Serial Interface Control Register */ |
284 |
#define TWCR _SFR_MEM8(0x74) |
285 |
|
286 |
/* Time Counter 1 Output Compare Register C */ |
287 |
#define OCR1C _SFR_MEM16(0x78) |
288 |
#define OCR1CL _SFR_MEM8(0x78) |
289 |
#define OCR1CH _SFR_MEM8(0x79) |
290 |
|
291 |
/* Timer/Counter 1 Control Register C */ |
292 |
#define TCCR1C _SFR_MEM8(0x7A) |
293 |
|
294 |
/* Extended Timer Interrupt Flag Register */ |
295 |
#define ETIFR _SFR_MEM8(0x7C) |
296 |
|
297 |
/* Extended Timer Interrupt Mask Register */ |
298 |
#define ETIMSK _SFR_MEM8(0x7D) |
299 |
|
300 |
/* Timer/Counter 3 Input Capture Register */ |
301 |
#define ICR3 _SFR_MEM16(0x80) |
302 |
#define ICR3L _SFR_MEM8(0x80) |
303 |
#define ICR3H _SFR_MEM8(0x81) |
304 |
|
305 |
/* Timer/Counter 3 Output Compare Register C */ |
306 |
#define OCR3C _SFR_MEM16(0x82) |
307 |
#define OCR3CL _SFR_MEM8(0x82) |
308 |
#define OCR3CH _SFR_MEM8(0x83) |
309 |
|
310 |
/* Timer/Counter 3 Output Compare Register B */ |
311 |
#define OCR3B _SFR_MEM16(0x84) |
312 |
#define OCR3BL _SFR_MEM8(0x84) |
313 |
#define OCR3BH _SFR_MEM8(0x85) |
314 |
|
315 |
/* Timer/Counter 3 Output Compare Register A */ |
316 |
#define OCR3A _SFR_MEM16(0x86) |
317 |
#define OCR3AL _SFR_MEM8(0x86) |
318 |
#define OCR3AH _SFR_MEM8(0x87) |
319 |
|
320 |
/* Timer/Counter 3 Counter Register */ |
321 |
#define TCNT3 _SFR_MEM16(0x88) |
322 |
#define TCNT3L _SFR_MEM8(0x88) |
323 |
#define TCNT3H _SFR_MEM8(0x89) |
324 |
|
325 |
/* Timer/Counter 3 Control Register B */ |
326 |
#define TCCR3B _SFR_MEM8(0x8A) |
327 |
|
328 |
/* Timer/Counter 3 Control Register A */ |
329 |
#define TCCR3A _SFR_MEM8(0x8B) |
330 |
|
331 |
/* Timer/Counter 3 Control Register C */ |
332 |
#define TCCR3C _SFR_MEM8(0x8C) |
333 |
|
334 |
/* USART0 Baud Rate Register High */ |
335 |
#define UBRR0H _SFR_MEM8(0x90) |
336 |
|
337 |
/* USART0 Control and Status Register C */ |
338 |
#define UCSR0C _SFR_MEM8(0x95) |
339 |
|
340 |
/* USART1 Baud Rate Register High */ |
341 |
#define UBRR1H _SFR_MEM8(0x98) |
342 |
|
343 |
/* USART1 Baud Rate Register Low*/ |
344 |
#define UBRR1L _SFR_MEM8(0x99) |
345 |
|
346 |
/* USART1 Control and Status Register B */ |
347 |
#define UCSR1B _SFR_MEM8(0x9A) |
348 |
|
349 |
/* USART1 Control and Status Register A */ |
350 |
#define UCSR1A _SFR_MEM8(0x9B) |
351 |
|
352 |
/* USART1 I/O Data Register */ |
353 |
#define UDR1 _SFR_MEM8(0x9C) |
354 |
|
355 |
/* USART1 Control and Status Register C */ |
356 |
#define UCSR1C _SFR_MEM8(0x9D) |
357 |
|
358 |
/* Interrupt vectors */ |
359 |
|
360 |
#define SIG_INTERRUPT0 _VECTOR(1) |
361 |
#define SIG_INTERRUPT1 _VECTOR(2) |
362 |
#define SIG_INTERRUPT2 _VECTOR(3) |
363 |
#define SIG_INTERRUPT3 _VECTOR(4) |
364 |
#define SIG_INTERRUPT4 _VECTOR(5) |
365 |
#define SIG_INTERRUPT5 _VECTOR(6) |
366 |
#define SIG_INTERRUPT6 _VECTOR(7) |
367 |
#define SIG_INTERRUPT7 _VECTOR(8) |
368 |
#define SIG_OUTPUT_COMPARE2 _VECTOR(9) |
369 |
#define SIG_OVERFLOW2 _VECTOR(10) |
370 |
#define SIG_INPUT_CAPTURE1 _VECTOR(11) |
371 |
#define SIG_OUTPUT_COMPARE1A _VECTOR(12) |
372 |
#define SIG_OUTPUT_COMPARE1B _VECTOR(13) |
373 |
#define SIG_OVERFLOW1 _VECTOR(14) |
374 |
#define SIG_OUTPUT_COMPARE0 _VECTOR(15) |
375 |
#define SIG_OVERFLOW0 _VECTOR(16) |
376 |
#define SIG_SPI _VECTOR(17) |
377 |
#define SIG_UART0_RECV _VECTOR(18) |
378 |
#define SIG_UART0_DATA _VECTOR(19) |
379 |
#define SIG_UART0_TRANS _VECTOR(20) |
380 |
#define SIG_ADC _VECTOR(21) |
381 |
#define SIG_EEPROM_READY _VECTOR(22) |
382 |
#define SIG_COMPARATOR _VECTOR(23) |
383 |
#define SIG_OUTPUT_COMPARE1C _VECTOR(24) |
384 |
#define SIG_INPUT_CAPTURE3 _VECTOR(25) |
385 |
#define SIG_OUTPUT_COMPARE3A _VECTOR(26) |
386 |
#define SIG_OUTPUT_COMPARE3B _VECTOR(27) |
387 |
#define SIG_OUTPUT_COMPARE3C _VECTOR(28) |
388 |
#define SIG_OVERFLOW3 _VECTOR(29) |
389 |
#define SIG_UART1_RECV _VECTOR(30) |
390 |
#define SIG_UART1_DATA _VECTOR(31) |
391 |
#define SIG_UART1_TRANS _VECTOR(32) |
392 |
#define SIG_2WIRE_SERIAL _VECTOR(33) |
393 |
#define SIG_SPM_READY _VECTOR(34) |
394 |
|
395 |
#define _VECTORS_SIZE 140 |
396 |
|
397 |
/* |
398 |
The Register Bit names are represented by their bit number (0-7). |
399 |
*/ |
400 |
|
401 |
/* 2-wire Control Register - TWCR */ |
402 |
#define TWINT 7 |
403 |
#define TWEA 6 |
404 |
#define TWSTA 5 |
405 |
#define TWSTO 4 |
406 |
#define TWWC 3 |
407 |
#define TWEN 2 |
408 |
#define TWIE 0 |
409 |
|
410 |
/* 2-wire Address Register - TWAR */ |
411 |
#define TWA6 7 |
412 |
#define TWA5 6 |
413 |
#define TWA4 5 |
414 |
#define TWA3 4 |
415 |
#define TWA2 3 |
416 |
#define TWA1 2 |
417 |
#define TWA0 1 |
418 |
#define TWGCE 0 |
419 |
|
420 |
/* 2-wire Status Register - TWSR */ |
421 |
#define TWS7 7 |
422 |
#define TWS6 6 |
423 |
#define TWS5 5 |
424 |
#define TWS4 4 |
425 |
#define TWS3 3 |
426 |
#define TWPS1 1 |
427 |
#define TWPS0 0 |
428 |
|
429 |
/* External Memory Control Register A - XMCRA */ |
430 |
#define SRL2 6 |
431 |
#define SRL1 5 |
432 |
#define SRL0 4 |
433 |
#define SRW01 3 |
434 |
#define SRW00 2 |
435 |
#define SRW11 1 |
436 |
|
437 |
/* External Memory Control Register B - XMCRA */ |
438 |
#define XMBK 7 |
439 |
#define XMM2 2 |
440 |
#define XMM1 1 |
441 |
#define XMM0 0 |
442 |
|
443 |
/* XDIV Divide control register - XDIV */ |
444 |
#define XDIVEN 7 |
445 |
#define XDIV6 6 |
446 |
#define XDIV5 5 |
447 |
#define XDIV4 4 |
448 |
#define XDIV3 3 |
449 |
#define XDIV2 2 |
450 |
#define XDIV1 1 |
451 |
#define XDIV0 0 |
452 |
|
453 |
/* RAM Page Z select register - RAMPZ */ |
454 |
#define RAMPZ0 0 |
455 |
|
456 |
/* External Interrupt Control Register A - EICRA */ |
457 |
#define ISC31 7 |
458 |
#define ISC30 6 |
459 |
#define ISC21 5 |
460 |
#define ISC20 4 |
461 |
#define ISC11 3 |
462 |
#define ISC10 2 |
463 |
#define ISC01 1 |
464 |
#define ISC00 0 |
465 |
|
466 |
/* External Interrupt Control Register B - EICRB */ |
467 |
#define ISC71 7 |
468 |
#define ISC70 6 |
469 |
#define ISC61 5 |
470 |
#define ISC60 4 |
471 |
#define ISC51 3 |
472 |
#define ISC50 2 |
473 |
#define ISC41 1 |
474 |
#define ISC40 0 |
475 |
|
476 |
/* Store Program Memory Control Register - SPMCSR, SPMCR */ |
477 |
#define SPMIE 7 |
478 |
#define RWWSB 6 |
479 |
#define RWWSRE 4 |
480 |
#define BLBSET 3 |
481 |
#define PGWRT 2 |
482 |
#define PGERS 1 |
483 |
#define SPMEN 0 |
484 |
|
485 |
/* External Interrupt MaSK register - EIMSK */ |
486 |
#define INT7 7 |
487 |
#define INT6 6 |
488 |
#define INT5 5 |
489 |
#define INT4 4 |
490 |
#define INT3 3 |
491 |
#define INT2 2 |
492 |
#define INT1 1 |
493 |
#define INT0 0 |
494 |
|
495 |
/* External Interrupt Flag Register - EIFR */ |
496 |
#define INTF7 7 |
497 |
#define INTF6 6 |
498 |
#define INTF5 5 |
499 |
#define INTF4 4 |
500 |
#define INTF3 3 |
501 |
#define INTF2 2 |
502 |
#define INTF1 1 |
503 |
#define INTF0 0 |
504 |
|
505 |
/* Timer/Counter Interrupt MaSK register - TIMSK */ |
506 |
#define OCIE2 7 |
507 |
#define TOIE2 6 |
508 |
#define TICIE1 5 |
509 |
#define OCIE1A 4 |
510 |
#define OCIE1B 3 |
511 |
#define TOIE1 2 |
512 |
#define OCIE0 1 |
513 |
#define TOIE0 0 |
514 |
|
515 |
/* Timer/Counter Interrupt Flag Register - TIFR */ |
516 |
#define OCF2 7 |
517 |
#define TOV2 6 |
518 |
#define ICF1 5 |
519 |
#define OCF1A 4 |
520 |
#define OCF1B 3 |
521 |
#define TOV1 2 |
522 |
#define OCF0 1 |
523 |
#define TOV0 0 |
524 |
|
525 |
/* Extended Timer Interrupt MaSK register - ETIMSK */ |
526 |
#define TICIE3 5 |
527 |
#define OCIE3A 4 |
528 |
#define OCIE3B 3 |
529 |
#define TOIE3 2 |
530 |
#define OCIE3C 1 |
531 |
#define OCIE1C 0 |
532 |
|
533 |
/* Extended Timer Interrupt Flag Register - ETIFR */ |
534 |
#define ICF3 5 |
535 |
#define OCF3A 4 |
536 |
#define OCF3B 3 |
537 |
#define TOV3 2 |
538 |
#define OCF3C 1 |
539 |
#define OCF1C 0 |
540 |
|
541 |
/* MCU general Control Register - MCUCR */ |
542 |
#define SRE 7 |
543 |
#define SRW 6 |
544 |
#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ |
545 |
#define SE 5 |
546 |
#define SM1 4 |
547 |
#define SM0 3 |
548 |
#define SM2 2 |
549 |
#define IVSEL 1 |
550 |
#define IVCE 0 |
551 |
|
552 |
/* MCU Status Register - MCUSR, MCUCSR */ |
553 |
#define JTD 7 |
554 |
#define JTRF 4 |
555 |
#define WDRF 3 |
556 |
#define BORF 2 |
557 |
#define EXTRF 1 |
558 |
#define PORF 0 |
559 |
|
560 |
/* Timer/Counter Control Register (generic) */ |
561 |
#define FOC 7 |
562 |
#define WGM0 6 |
563 |
#define COM1 5 |
564 |
#define COM0 4 |
565 |
#define WGM1 3 |
566 |
#define CS2 2 |
567 |
#define CS1 1 |
568 |
#define CS0 0 |
569 |
|
570 |
/* Timer/Counter 0 Control Register - TCCR0 */ |
571 |
#define FOC0 7 |
572 |
#define WGM00 6 |
573 |
#define COM01 5 |
574 |
#define COM00 4 |
575 |
#define WGM01 3 |
576 |
#define CS02 2 |
577 |
#define CS01 1 |
578 |
#define CS00 0 |
579 |
|
580 |
/* Timer/Counter 2 Control Register - TCCR2 */ |
581 |
#define FOC2 7 |
582 |
#define WGM20 6 |
583 |
#define COM21 5 |
584 |
#define COM20 4 |
585 |
#define WGM21 3 |
586 |
#define CS22 2 |
587 |
#define CS21 1 |
588 |
#define CS20 0 |
589 |
|
590 |
/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ |
591 |
#define AS0 3 |
592 |
#define TCN0UB 2 |
593 |
#define OCR0UB 1 |
594 |
#define TCR0UB 0 |
595 |
|
596 |
/* Timer/Counter Control Register A (generic) */ |
597 |
#define COMA1 7 |
598 |
#define COMA0 6 |
599 |
#define COMB1 5 |
600 |
#define COMB0 4 |
601 |
#define COMC1 3 |
602 |
#define COMC0 2 |
603 |
#define WGMA1 1 |
604 |
#define WGMA0 0 |
605 |
|
606 |
/* Timer/Counter 1 Control and Status Register A - TCCR1A */ |
607 |
#define COM1A1 7 |
608 |
#define COM1A0 6 |
609 |
#define COM1B1 5 |
610 |
#define COM1B0 4 |
611 |
#define COM1C1 3 |
612 |
#define COM1C0 2 |
613 |
#define WGM11 1 |
614 |
#define WGM10 0 |
615 |
|
616 |
/* Timer/Counter 3 Control and Status Register A - TCCR3A */ |
617 |
#define COM3A1 7 |
618 |
#define COM3A0 6 |
619 |
#define COM3B1 5 |
620 |
#define COM3B0 4 |
621 |
#define COM3C1 3 |
622 |
#define COM3C0 2 |
623 |
#define WGM31 1 |
624 |
#define WGM30 0 |
625 |
|
626 |
/* Timer/Counter Control and Status Register B (generic) */ |
627 |
#define ICNC 7 |
628 |
#define ICES 6 |
629 |
#define WGMB3 4 |
630 |
#define WGMB2 3 |
631 |
#define CSB2 2 |
632 |
#define CSB1 1 |
633 |
#define CSB0 0 |
634 |
|
635 |
/* Timer/Counter 1 Control and Status Register B - TCCR1B */ |
636 |
#define ICNC1 7 |
637 |
#define ICES1 6 |
638 |
#define WGM13 4 |
639 |
#define WGM12 3 |
640 |
#define CS12 2 |
641 |
#define CS11 1 |
642 |
#define CS10 0 |
643 |
|
644 |
/* Timer/Counter 3 Control and Status Register B - TCCR3B */ |
645 |
#define ICNC3 7 |
646 |
#define ICES3 6 |
647 |
#define WGM33 4 |
648 |
#define WGM32 3 |
649 |
#define CS32 2 |
650 |
#define CS31 1 |
651 |
#define CS30 0 |
652 |
|
653 |
/* Timer/Counter Control Register C (generic) */ |
654 |
#define FOCA 7 |
655 |
#define FOCB 6 |
656 |
#define FOCC 5 |
657 |
|
658 |
/* Timer/Counter 3 Control Register C - TCCR3C */ |
659 |
#define FOC3A 7 |
660 |
#define FOC3B 6 |
661 |
#define FOC3C 5 |
662 |
|
663 |
/* Timer/Counter 1 Control Register C - TCCR1C */ |
664 |
#define FOC1A 7 |
665 |
#define FOC1B 6 |
666 |
#define FOC1C 5 |
667 |
|
668 |
/* On-chip Debug Register - OCDR */ |
669 |
#define IDRD 7 |
670 |
#define OCDR7 7 |
671 |
#define OCDR6 6 |
672 |
#define OCDR5 5 |
673 |
#define OCDR4 4 |
674 |
#define OCDR3 3 |
675 |
#define OCDR2 2 |
676 |
#define OCDR1 1 |
677 |
#define OCDR0 0 |
678 |
|
679 |
/* Watchdog Timer Control Register - WDTCR */ |
680 |
#define WDCE 4 |
681 |
#define WDE 3 |
682 |
#define WDP2 2 |
683 |
#define WDP1 1 |
684 |
#define WDP0 0 |
685 |
|
686 |
/* Special Function I/O Register - SFIOR */ |
687 |
#define TSM 7 |
688 |
#define ADHSM 4 |
689 |
#define ACME 3 |
690 |
#define PUD 2 |
691 |
#define PSR0 1 |
692 |
#define PSR321 0 |
693 |
|
694 |
/* EEPROM Control Register - EECR */ |
695 |
#define EERIE 3 |
696 |
#define EEMWE 2 |
697 |
#define EEWE 1 |
698 |
#define EERE 0 |
699 |
|
700 |
/* Port Data Register (generic) */ |
701 |
#define PORT7 7 |
702 |
#define PORT6 6 |
703 |
#define PORT5 5 |
704 |
#define PORT4 4 |
705 |
#define PORT3 3 |
706 |
#define PORT2 2 |
707 |
#define PORT1 1 |
708 |
#define PORT0 0 |
709 |
|
710 |
/* Port Data Direction Register (generic) */ |
711 |
#define DD7 7 |
712 |
#define DD6 6 |
713 |
#define DD5 5 |
714 |
#define DD4 4 |
715 |
#define DD3 3 |
716 |
#define DD2 2 |
717 |
#define DD1 1 |
718 |
#define DD0 0 |
719 |
|
720 |
/* Port Input Pins (generic) */ |
721 |
#define PIN7 7 |
722 |
#define PIN6 6 |
723 |
#define PIN5 5 |
724 |
#define PIN4 4 |
725 |
#define PIN3 3 |
726 |
#define PIN2 2 |
727 |
#define PIN1 1 |
728 |
#define PIN0 0 |
729 |
|
730 |
/* Status Register - SREG */ |
731 |
#define SREG_I 7 |
732 |
#define SREG_T 6 |
733 |
#define SREG_H 5 |
734 |
#define SREG_S 4 |
735 |
#define SREG_V 3 |
736 |
#define SREG_N 2 |
737 |
#define SREG_Z 1 |
738 |
#define SREG_C 0 |
739 |
|
740 |
/* SPI Status Register - SPSR */ |
741 |
#define SPIF 7 |
742 |
#define WCOL 6 |
743 |
#define SPI2X 0 |
744 |
|
745 |
/* SPI Control Register - SPCR */ |
746 |
#define SPIE 7 |
747 |
#define SPE 6 |
748 |
#define DORD 5 |
749 |
#define MSTR 4 |
750 |
#define CPOL 3 |
751 |
#define CPHA 2 |
752 |
#define SPR1 1 |
753 |
#define SPR0 0 |
754 |
|
755 |
/* USART Register C (generic) */ |
756 |
#define UMSEL 6 |
757 |
#define UPM1 5 |
758 |
#define UPM0 4 |
759 |
#define USBS 3 |
760 |
#define UCSZ1 2 |
761 |
#define UCSZ0 1 |
762 |
#define UCPOL 0 |
763 |
|
764 |
/* USART1 Register C - UCSR1C */ |
765 |
#define UMSEL1 6 |
766 |
#define UPM11 5 |
767 |
#define UPM10 4 |
768 |
#define USBS1 3 |
769 |
#define UCSZ11 2 |
770 |
#define UCSZ10 1 |
771 |
#define UCPOL1 0 |
772 |
|
773 |
/* USART0 Register C - UCSR0C */ |
774 |
#define UMSEL0 6 |
775 |
#define UPM01 5 |
776 |
#define UPM00 4 |
777 |
#define USBS0 3 |
778 |
#define UCSZ01 2 |
779 |
#define UCSZ00 1 |
780 |
#define UCPOL0 0 |
781 |
|
782 |
/* USART Status Register A (generic) */ |
783 |
#define RXC 7 |
784 |
#define TXC 6 |
785 |
#define UDRE 5 |
786 |
#define FE 4 |
787 |
#define DOR 3 |
788 |
#define UPE 2 |
789 |
#define U2X 1 |
790 |
#define MPCM 0 |
791 |
|
792 |
/* USART1 Status Register A - UCSR1A */ |
793 |
#define RXC1 7 |
794 |
#define TXC1 6 |
795 |
#define UDRE1 5 |
796 |
#define FE1 4 |
797 |
#define DOR1 3 |
798 |
#define UPE1 2 |
799 |
#define U2X1 1 |
800 |
#define MPCM1 0 |
801 |
|
802 |
/* USART0 Status Register A - UCSR0A */ |
803 |
#define RXC0 7 |
804 |
#define TXC0 6 |
805 |
#define UDRE0 5 |
806 |
#define FE0 4 |
807 |
#define DOR0 3 |
808 |
#define UPE0 2 |
809 |
#define U2X0 1 |
810 |
#define MPCM0 0 |
811 |
|
812 |
/* USART Control Register B (generic) */ |
813 |
#define RXCIE 7 |
814 |
#define TXCIE 6 |
815 |
#define UDRIE 5 |
816 |
#define RXEN 4 |
817 |
#define TXEN 3 |
818 |
#define UCSZ 2 |
819 |
#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ |
820 |
#define RXB8 1 |
821 |
#define TXB8 0 |
822 |
|
823 |
/* USART1 Control Register B - UCSR1B */ |
824 |
#define RXCIE1 7 |
825 |
#define TXCIE1 6 |
826 |
#define UDRIE1 5 |
827 |
#define RXEN1 4 |
828 |
#define TXEN1 3 |
829 |
#define UCSZ12 2 |
830 |
#define RXB81 1 |
831 |
#define TXB81 0 |
832 |
|
833 |
/* USART0 Control Register B - UCSR0B */ |
834 |
#define RXCIE0 7 |
835 |
#define TXCIE0 6 |
836 |
#define UDRIE0 5 |
837 |
#define RXEN0 4 |
838 |
#define TXEN0 3 |
839 |
#define UCSZ02 2 |
840 |
#define RXB80 1 |
841 |
#define TXB80 0 |
842 |
|
843 |
/* Analog Comparator Control and Status Register - ACSR */ |
844 |
#define ACD 7 |
845 |
#define ACBG 6 |
846 |
#define ACO 5 |
847 |
#define ACI 4 |
848 |
#define ACIE 3 |
849 |
#define ACIC 2 |
850 |
#define ACIS1 1 |
851 |
#define ACIS0 0 |
852 |
|
853 |
/* ADC Control and status register - ADCSRA */ |
854 |
#define ADEN 7 |
855 |
#define ADSC 6 |
856 |
#define ADFR 5 |
857 |
#define ADIF 4 |
858 |
#define ADIE 3 |
859 |
#define ADPS2 2 |
860 |
#define ADPS1 1 |
861 |
#define ADPS0 0 |
862 |
|
863 |
/* ADC Multiplexer select - ADMUX */ |
864 |
#define REFS1 7 |
865 |
#define REFS0 6 |
866 |
#define ADLAR 5 |
867 |
#define MUX4 4 |
868 |
#define MUX3 3 |
869 |
#define MUX2 2 |
870 |
#define MUX1 1 |
871 |
#define MUX0 0 |
872 |
|
873 |
/* Port A Data Register - PORTA */ |
874 |
#define PORTA7 7 |
875 |
#define PORTA6 6 |
876 |
#define PORTA5 5 |
877 |
#define PORTA4 4 |
878 |
#define PORTA3 3 |
879 |
#define PORTA2 2 |
880 |
#define PORTA1 1 |
881 |
#define PORTA0 0 |
882 |
|
883 |
/* Port A Data Direction Register - DDRA */ |
884 |
#define DDA7 7 |
885 |
#define DDA6 6 |
886 |
#define DDA5 5 |
887 |
#define DDA4 4 |
888 |
#define DDA3 3 |
889 |
#define DDA2 2 |
890 |
#define DDA1 1 |
891 |
#define DDA0 0 |
892 |
|
893 |
/* Port A Input Pins - PINA */ |
894 |
#define PINA7 7 |
895 |
#define PINA6 6 |
896 |
#define PINA5 5 |
897 |
#define PINA4 4 |
898 |
#define PINA3 3 |
899 |
#define PINA2 2 |
900 |
#define PINA1 1 |
901 |
#define PINA0 0 |
902 |
|
903 |
/* Port B Data Register - PORTB */ |
904 |
#define PORTB7 7 |
905 |
#define PORTB6 6 |
906 |
#define PORTB5 5 |
907 |
#define PORTB4 4 |
908 |
#define PORTB3 3 |
909 |
#define PORTB2 2 |
910 |
#define PORTB1 1 |
911 |
#define PORTB0 0 |
912 |
|
913 |
/* Port B Data Direction Register - DDRB */ |
914 |
#define DDB7 7 |
915 |
#define DDB6 6 |
916 |
#define DDB5 5 |
917 |
#define DDB4 4 |
918 |
#define DDB3 3 |
919 |
#define DDB2 2 |
920 |
#define DDB1 1 |
921 |
#define DDB0 0 |
922 |
|
923 |
/* Port B Input Pins - PINB */ |
924 |
#define PINB7 7 |
925 |
#define PINB6 6 |
926 |
#define PINB5 5 |
927 |
#define PINB4 4 |
928 |
#define PINB3 3 |
929 |
#define PINB2 2 |
930 |
#define PINB1 1 |
931 |
#define PINB0 0 |
932 |
|
933 |
/* Port C Data Register - PORTC */ |
934 |
#define PORTC7 7 |
935 |
#define PORTC6 6 |
936 |
#define PORTC5 5 |
937 |
#define PORTC4 4 |
938 |
#define PORTC3 3 |
939 |
#define PORTC2 2 |
940 |
#define PORTC1 1 |
941 |
#define PORTC0 0 |
942 |
|
943 |
/* Port C Data Direction Register - DDRC */ |
944 |
#define DDC7 7 |
945 |
#define DDC6 6 |
946 |
#define DDC5 5 |
947 |
#define DDC4 4 |
948 |
#define DDC3 3 |
949 |
#define DDC2 2 |
950 |
#define DDC1 1 |
951 |
#define DDC0 0 |
952 |
|
953 |
/* Port C Input Pins - PINC */ |
954 |
#define PINC7 7 |
955 |
#define PINC6 6 |
956 |
#define PINC5 5 |
957 |
#define PINC4 4 |
958 |
#define PINC3 3 |
959 |
#define PINC2 2 |
960 |
#define PINC1 1 |
961 |
#define PINC0 0 |
962 |
|
963 |
/* Port D Data Register - PORTD */ |
964 |
#define PORTD7 7 |
965 |
#define PORTD6 6 |
966 |
#define PORTD5 5 |
967 |
#define PORTD4 4 |
968 |
#define PORTD3 3 |
969 |
#define PORTD2 2 |
970 |
#define PORTD1 1 |
971 |
#define PORTD0 0 |
972 |
|
973 |
/* Port D Data Direction Register - DDRD */ |
974 |
#define DDD7 7 |
975 |
#define DDD6 6 |
976 |
#define DDD5 5 |
977 |
#define DDD4 4 |
978 |
#define DDD3 3 |
979 |
#define DDD2 2 |
980 |
#define DDD1 1 |
981 |
#define DDD0 0 |
982 |
|
983 |
/* Port D Input Pins - PIND */ |
984 |
#define PIND7 7 |
985 |
#define PIND6 6 |
986 |
#define PIND5 5 |
987 |
#define PIND4 4 |
988 |
#define PIND3 3 |
989 |
#define PIND2 2 |
990 |
#define PIND1 1 |
991 |
#define PIND0 0 |
992 |
|
993 |
/* Port E Data Register - PORTE */ |
994 |
#define PORTE7 7 |
995 |
#define PORTE6 6 |
996 |
#define PORTE5 5 |
997 |
#define PORTE4 4 |
998 |
#define PORTE3 3 |
999 |
#define PORTE2 2 |
1000 |
#define PORTE1 1 |
1001 |
#define PORTE0 0 |
1002 |
|
1003 |
/* Port E Data Direction Register - DDRE */ |
1004 |
#define DDE7 7 |
1005 |
#define DDE6 6 |
1006 |
#define DDE5 5 |
1007 |
#define DDE4 4 |
1008 |
#define DDE3 3 |
1009 |
#define DDE2 2 |
1010 |
#define DDE1 1 |
1011 |
#define DDE0 0 |
1012 |
|
1013 |
/* Port E Input Pins - PINE */ |
1014 |
#define PINE7 7 |
1015 |
#define PINE6 6 |
1016 |
#define PINE5 5 |
1017 |
#define PINE4 4 |
1018 |
#define PINE3 3 |
1019 |
#define PINE2 2 |
1020 |
#define PINE1 1 |
1021 |
#define PINE0 0 |
1022 |
|
1023 |
/* Port F Data Register - PORTF */ |
1024 |
#define PORTF7 7 |
1025 |
#define PORTF6 6 |
1026 |
#define PORTF5 5 |
1027 |
#define PORTF4 4 |
1028 |
#define PORTF3 3 |
1029 |
#define PORTF2 2 |
1030 |
#define PORTF1 1 |
1031 |
#define PORTF0 0 |
1032 |
|
1033 |
/* Port F Data Direction Register - DDRF */ |
1034 |
#define DDF7 7 |
1035 |
#define DDF6 6 |
1036 |
#define DDF5 5 |
1037 |
#define DDF4 4 |
1038 |
#define DDF3 3 |
1039 |
#define DDF2 2 |
1040 |
#define DDF1 1 |
1041 |
#define DDF0 0 |
1042 |
|
1043 |
/* Port F Input Pins - PINF */ |
1044 |
#define PINF7 7 |
1045 |
#define PINF6 6 |
1046 |
#define PINF5 5 |
1047 |
#define PINF4 4 |
1048 |
#define PINF3 3 |
1049 |
#define PINF2 2 |
1050 |
#define PINF1 1 |
1051 |
#define PINF0 0 |
1052 |
|
1053 |
/* Port G Data Register - PORTG */ |
1054 |
#define PORTG4 4 |
1055 |
#define PORTG3 3 |
1056 |
#define PORTG2 2 |
1057 |
#define PORTG1 1 |
1058 |
#define PORTG0 0 |
1059 |
|
1060 |
/* Port G Data Direction Register - DDRG */ |
1061 |
#define DDG4 4 |
1062 |
#define DDG3 3 |
1063 |
#define DDG2 2 |
1064 |
#define DDG1 1 |
1065 |
#define DDG0 0 |
1066 |
|
1067 |
/* Port G Input Pins - PING */ |
1068 |
#define PING4 4 |
1069 |
#define PING3 3 |
1070 |
#define PING2 2 |
1071 |
#define PING1 1 |
1072 |
#define PING0 0 |
1073 |
|
1074 |
/* Pointer definition */ |
1075 |
#define XL r26 |
1076 |
#define XH r27 |
1077 |
#define YL r28 |
1078 |
#define YH r29 |
1079 |
#define ZL r30 |
1080 |
#define ZH r31 |
1081 |
|
1082 |
/* Constants */ |
1083 |
#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ |
1084 |
#define XRAMEND 0xFFFF |
1085 |
#define E2END 0x0FFF |
1086 |
#define FLASHEND 0x1FFFF |
1087 |
|
1088 |
#endif /* _AVR_IOM128_H_ */ |