/[avr-libc]/avr-libc/include/avr/iom169.h
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Diff of /avr-libc/include/avr/iom169.h

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revision 1.13 by arcanum, Fri Jun 13 20:43:08 2003 UTC revision 1.13.2.1 by troth, Wed Apr 14 16:54:47 2004 UTC
# Line 1  Line 1 
1  /* Copyright (c) 2002, Juergen Schilling <juergen.schilling@honeywell.com>  /* Copyright (c) 2002, 2003, 2004
2       Juergen Schilling <juergen.schilling@honeywell.com>
3     All rights reserved.     All rights reserved.
4    
5     Redistribution and use in source and binary forms, with or without     Redistribution and use in source and binary forms, with or without
# Line 27  Line 28 
28    
29  /* iom169.h - definitions for ATmega169 */  /* iom169.h - definitions for ATmega169 */
30    
31    /* This should be up to date with data sheet version 2514J-AVR-12/03. */
32    
33  #ifndef _AVR_IOM169_H_  #ifndef _AVR_IOM169_H_
34  #define _AVR_IOM169_H_ 1  #define _AVR_IOM169_H_ 1
35    
# Line 230  Line 233 
233  #define ICR1H  _SFR_MEM8(0x87)  #define ICR1H  _SFR_MEM8(0x87)
234    
235  /* Timer/Counter1 Output Compare Register A */  /* Timer/Counter1 Output Compare Register A */
236  #define OCRA1  _SFR_MEM16(0x88)  #define OCR1A  _SFR_MEM16(0x88)
237  #define OCRA1L _SFR_MEM8(0x88)  #define OCR1AL _SFR_MEM8(0x88)
238  #define OCRA1H _SFR_MEM8(0x89)  #define OCR1AH _SFR_MEM8(0x89)
239    
240  /* Timer/Counter1 Output Compare Registare B */  /* Timer/Counter1 Output Compare Registare B */
241  #define OCRB1  _SFR_MEM16(0x8A)  #define OCR1B  _SFR_MEM16(0x8A)
242  #define OCRB1L _SFR_MEM8(0x8A)  #define OCR1BL _SFR_MEM8(0x8A)
243  #define OCRB1H _SFR_MEM8(0x8B)  #define OCR1BH _SFR_MEM8(0x8B)
244    
245  /* Timer/Counter2 Control Register A */  /* Timer/Counter2 Control Register A */
246  #define TCCR2A _SFR_MEM8(0xB0)  #define TCCR2A _SFR_MEM8(0xB0)
# Line 261  Line 264 
264  #define USIDR  _SFR_MEM8(0xBA)  #define USIDR  _SFR_MEM8(0xBA)
265    
266  /* USART0 Control and Status Register A */  /* USART0 Control and Status Register A */
267  #define UCSR0A _SFR_MEM8(0xC0)  #define UCSRA  _SFR_MEM8(0xC0)
268    #define UCSR0A UCSRA            /* For compatibility with previous releases. */
269    
270  /* USART0 Control and Status Register B */  /* USART0 Control and Status Register B */
271  #define UCSR0B _SFR_MEM8(0xC1)  #define UCSRB  _SFR_MEM8(0xC1)
272    #define UCSR0B UCSRB            /* For compatibility with previous releases. */
273    
274  /* USART0 Control and Status Register C */  /* USART0 Control and Status Register C */
275  #define UCSR0C _SFR_MEM8(0xC2)  #define UCSRC  _SFR_MEM8(0xC2)
276    #define UCSR0C UCSRC            /* For compatibility with previous releases. */
277    
278  /* USART0 Baud Rate Register */  /* USART0 Baud Rate Register */
279  #define UBRR0  _SFR_MEM16(0xC4)  #define UBRR   _SFR_MEM16(0xC4)
280  #define UBRR0L _SFR_MEM8(0xC4)  #define UBRRL  _SFR_MEM8(0xC4)
281  #define UBRR0H _SFR_MEM8(0xC5)  #define UBRRH  _SFR_MEM8(0xC5)
282    
283    /* For compatibility with previous releases. */
284    #define UBRR0  UBRR
285    #define UBRR0L UBRRL
286    #define UBRR0H UBRRH
287    
288  /* USART0 I/O Data Register */  /* USART0 I/O Data Register */
289  #define UDR0   _SFR_MEM8(0xC6)  #define UDR    _SFR_MEM8(0xC6)
290    #define UDR0   UDR             /* For compatibility with previous releases. */
291    
292  /* LCD Control and Status Register A */  /* LCD Control and Status Register A */
293  #define LCDCRA _SFR_MEM8(0xE4)  #define LCDCRA _SFR_MEM8(0xE4)
# Line 592  Line 604 
604   */   */
605    
606  /* PORTG */  /* PORTG */
 #define PG5 5  
607  #define PG4 4  #define PG4 4
608  #define PG3 3  #define PG3 3
609  #define PG2 2  #define PG2 2
# Line 724  Line 735 
735  #define SPMEN  0  #define SPMEN  0
736    
737  /* WDTCR */  /* WDTCR */
738  #define WDTCE   4  #define WDCE    4
739    #define WDTCE   WDCE           /* For compatibility with previous releases. */
740  #define WDE        3  #define WDE        3
741  #define WDP2    2  #define WDP2    2
742  #define WDP1    1  #define WDP1    1
# Line 737  Line 749 
749  #define CLKPS1 1  #define CLKPS1 1
750  #define CLKPS0 0  #define CLKPS0 0
751    
752    /* EICRA */
753    #define ISC01  1
754    #define ISC00  0
755    
756  /* PCMSK0 */  /* PCMSK0 */
757  #define PCINT7 7  #define PCINT7 7
758  #define PCINT6 6  #define PCINT6 6
# Line 782  Line 798 
798  #define ADPS0  0  #define ADPS0  0
799    
800  /* ADCSRB */  /* ADCSRB */
 #define ADHSM  7  
801  #define ACME   6  #define ACME   6
802  #define ADTS2  2  #define ADTS2  2
803  #define ADTS1  1  #define ADTS1  1
# Line 798  Line 813 
813  #define MUX1   1  #define MUX1   1
814  #define MUX0   0  #define MUX0   0
815    
816  /* DIDR0 */  /* DIDR1 */
817  #define AIN1D  1  #define AIN1D  1
818  #define AIN0D  0  #define AIN0D  0
819    
820  /* DIDR1 */  /* DIDR0 */
821  #define ADC7D  7  #define ADC7D  7
822  #define ADC6D  6  #define ADC6D  6
823  #define ADC5D  5  #define ADC5D  5
# Line 870  Line 885 
885  #define USICNT1 1  #define USICNT1 1
886  #define USICNT0 0  #define USICNT0 0
887    
888  /* UCSR0A */  /* UCSRA */
889  #define RXC0    7  #define RXC     7
890  #define TXC0    6  #define TXC     6
891  #define UDRE0   5  #define UDRE    5
892  #define FE0        4  #define FE      4
893  #define DOR0    3  #define DOR     3
894  #define UPE0    2  #define UPE     2
895  #define U2X0   1  #define U2X     1
896  #define MPCM0   0  #define MPCM    0
897    
898  /* UCSR0B */  /* UCSR0A -- For compatibility with previous releases. */
899  #define RXCIE0  7  #define RXC0    RXC
900  #define TXCIE0  6  #define TXC0    TXC
901  #define UDRIE0  5  #define UDRE0   UDRE
902  #define RXEN0   4  #define FE0     FE
903  #define TXEN0   3  #define DOR0    DOR
904  #define UCSZ02 2  #define UPE0    UPE
905  #define RXB80   1  #define U2X0    U2X
906  #define TXB80   0  #define MPCM0   MPCM
907    
908  /* UCSR0C */  /* UCSRB */
909  #define UMSEL0 6  #define RXCIE   7
910  #define UPM01  5  #define TXCIE   6
911  #define UPM00  4  #define UDRIE   5
912  #define USBS0  3  #define RXEN    4
913  #define UCSZ01 2  #define TXEN    3
914  #define UCSZ00 1  #define UCSZ2   2
915  #define UCPOL0 0  #define RXB8    1
916    #define TXB8    0
917    
918    /* UCSR0B -- For compatibility with previous releases. */
919    #define RXCIE0  RXCIE
920    #define TXCIE0  TXCIE
921    #define UDRIE0  UDRIE
922    #define RXEN0   RXEN
923    #define TXEN0   TXEN
924    #define UCSZ02  UCSZ2
925    #define RXB80   RXB8
926    #define TXB80   TXB8
927    
928    /* UCSRC */
929    #define UMSEL   6
930    #define UPM1    5
931    #define UPM0    4
932    #define USBS    3
933    #define UCSZ1   2
934    #define UCSZ0   1
935    #define UCPOL   0
936    
937    /* UCSR0C -- For compatibility with previous releases. */
938    #define UMSEL0  UMSEL
939    #define UPM01   UPM1
940    #define UPM00   UPM0
941    #define USBS0   USBS
942    #define UCSZ01  UCSZ1
943    #define UCSZ00  UCSZ0
944    #define UCPOL0  UCPOL
945    
946  /* LCDCRA */  /* LCDCRA */
947  #define LCDEN  7  #define LCDEN  7

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