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/* Copyright (c) 2002, Juergen Schilling <juergen.schilling@honeywell.com> |
/* Copyright (c) 2002, 2003, 2004 |
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Juergen Schilling <juergen.schilling@honeywell.com> |
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All rights reserved. |
All rights reserved. |
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Redistribution and use in source and binary forms, with or without |
Redistribution and use in source and binary forms, with or without |
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/* iom169.h - definitions for ATmega169 */ |
/* iom169.h - definitions for ATmega169 */ |
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/* This should be up to date with data sheet version 2514J-AVR-12/03. */ |
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#ifndef _AVR_IOM169_H_ |
#ifndef _AVR_IOM169_H_ |
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#define _AVR_IOM169_H_ 1 |
#define _AVR_IOM169_H_ 1 |
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#define ICR1H _SFR_MEM8(0x87) |
#define ICR1H _SFR_MEM8(0x87) |
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/* Timer/Counter1 Output Compare Register A */ |
/* Timer/Counter1 Output Compare Register A */ |
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#define OCRA1 _SFR_MEM16(0x88) |
#define OCR1A _SFR_MEM16(0x88) |
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#define OCRA1L _SFR_MEM8(0x88) |
#define OCR1AL _SFR_MEM8(0x88) |
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#define OCRA1H _SFR_MEM8(0x89) |
#define OCR1AH _SFR_MEM8(0x89) |
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/* Timer/Counter1 Output Compare Registare B */ |
/* Timer/Counter1 Output Compare Registare B */ |
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#define OCRB1 _SFR_MEM16(0x8A) |
#define OCR1B _SFR_MEM16(0x8A) |
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#define OCRB1L _SFR_MEM8(0x8A) |
#define OCR1BL _SFR_MEM8(0x8A) |
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#define OCRB1H _SFR_MEM8(0x8B) |
#define OCR1BH _SFR_MEM8(0x8B) |
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/* Timer/Counter2 Control Register A */ |
/* Timer/Counter2 Control Register A */ |
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#define TCCR2A _SFR_MEM8(0xB0) |
#define TCCR2A _SFR_MEM8(0xB0) |
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#define USIDR _SFR_MEM8(0xBA) |
#define USIDR _SFR_MEM8(0xBA) |
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/* USART0 Control and Status Register A */ |
/* USART0 Control and Status Register A */ |
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#define UCSR0A _SFR_MEM8(0xC0) |
#define UCSRA _SFR_MEM8(0xC0) |
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#define UCSR0A UCSRA /* For compatibility with previous releases. */ |
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/* USART0 Control and Status Register B */ |
/* USART0 Control and Status Register B */ |
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#define UCSR0B _SFR_MEM8(0xC1) |
#define UCSRB _SFR_MEM8(0xC1) |
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#define UCSR0B UCSRB /* For compatibility with previous releases. */ |
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/* USART0 Control and Status Register C */ |
/* USART0 Control and Status Register C */ |
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#define UCSR0C _SFR_MEM8(0xC2) |
#define UCSRC _SFR_MEM8(0xC2) |
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#define UCSR0C UCSRC /* For compatibility with previous releases. */ |
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/* USART0 Baud Rate Register */ |
/* USART0 Baud Rate Register */ |
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#define UBRR0 _SFR_MEM16(0xC4) |
#define UBRR _SFR_MEM16(0xC4) |
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#define UBRR0L _SFR_MEM8(0xC4) |
#define UBRRL _SFR_MEM8(0xC4) |
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#define UBRR0H _SFR_MEM8(0xC5) |
#define UBRRH _SFR_MEM8(0xC5) |
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/* For compatibility with previous releases. */ |
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#define UBRR0 UBRR |
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#define UBRR0L UBRRL |
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#define UBRR0H UBRRH |
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/* USART0 I/O Data Register */ |
/* USART0 I/O Data Register */ |
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#define UDR0 _SFR_MEM8(0xC6) |
#define UDR _SFR_MEM8(0xC6) |
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#define UDR0 UDR /* For compatibility with previous releases. */ |
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/* LCD Control and Status Register A */ |
/* LCD Control and Status Register A */ |
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#define LCDCRA _SFR_MEM8(0xE4) |
#define LCDCRA _SFR_MEM8(0xE4) |
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*/ |
*/ |
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/* PORTG */ |
/* PORTG */ |
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#define PG5 5 |
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#define PG4 4 |
#define PG4 4 |
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#define PG3 3 |
#define PG3 3 |
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#define PG2 2 |
#define PG2 2 |
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#define SPMEN 0 |
#define SPMEN 0 |
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/* WDTCR */ |
/* WDTCR */ |
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#define WDTCE 4 |
#define WDCE 4 |
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#define WDTCE WDCE /* For compatibility with previous releases. */ |
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#define WDE 3 |
#define WDE 3 |
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#define WDP2 2 |
#define WDP2 2 |
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#define WDP1 1 |
#define WDP1 1 |
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#define CLKPS1 1 |
#define CLKPS1 1 |
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#define CLKPS0 0 |
#define CLKPS0 0 |
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/* EICRA */ |
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#define ISC01 1 |
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#define ISC00 0 |
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/* PCMSK0 */ |
/* PCMSK0 */ |
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#define PCINT7 7 |
#define PCINT7 7 |
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#define PCINT6 6 |
#define PCINT6 6 |
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#define ADPS0 0 |
#define ADPS0 0 |
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/* ADCSRB */ |
/* ADCSRB */ |
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#define ADHSM 7 |
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#define ACME 6 |
#define ACME 6 |
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#define ADTS2 2 |
#define ADTS2 2 |
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#define ADTS1 1 |
#define ADTS1 1 |
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#define MUX1 1 |
#define MUX1 1 |
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#define MUX0 0 |
#define MUX0 0 |
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/* DIDR0 */ |
/* DIDR1 */ |
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#define AIN1D 1 |
#define AIN1D 1 |
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#define AIN0D 0 |
#define AIN0D 0 |
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/* DIDR1 */ |
/* DIDR0 */ |
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#define ADC7D 7 |
#define ADC7D 7 |
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#define ADC6D 6 |
#define ADC6D 6 |
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#define ADC5D 5 |
#define ADC5D 5 |
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#define USICNT1 1 |
#define USICNT1 1 |
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#define USICNT0 0 |
#define USICNT0 0 |
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/* UCSR0A */ |
/* UCSRA */ |
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#define RXC0 7 |
#define RXC 7 |
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#define TXC0 6 |
#define TXC 6 |
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#define UDRE0 5 |
#define UDRE 5 |
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#define FE0 4 |
#define FE 4 |
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#define DOR0 3 |
#define DOR 3 |
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#define UPE0 2 |
#define UPE 2 |
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#define U2X0 1 |
#define U2X 1 |
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#define MPCM0 0 |
#define MPCM 0 |
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/* UCSR0B */ |
/* UCSR0A -- For compatibility with previous releases. */ |
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#define RXCIE0 7 |
#define RXC0 RXC |
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#define TXCIE0 6 |
#define TXC0 TXC |
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#define UDRIE0 5 |
#define UDRE0 UDRE |
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#define RXEN0 4 |
#define FE0 FE |
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#define TXEN0 3 |
#define DOR0 DOR |
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#define UCSZ02 2 |
#define UPE0 UPE |
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#define RXB80 1 |
#define U2X0 U2X |
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#define TXB80 0 |
#define MPCM0 MPCM |
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/* UCSR0C */ |
/* UCSRB */ |
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#define UMSEL0 6 |
#define RXCIE 7 |
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#define UPM01 5 |
#define TXCIE 6 |
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#define UPM00 4 |
#define UDRIE 5 |
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#define USBS0 3 |
#define RXEN 4 |
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#define UCSZ01 2 |
#define TXEN 3 |
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#define UCSZ00 1 |
#define UCSZ2 2 |
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#define UCPOL0 0 |
#define RXB8 1 |
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#define TXB8 0 |
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/* UCSR0B -- For compatibility with previous releases. */ |
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#define RXCIE0 RXCIE |
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#define TXCIE0 TXCIE |
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#define UDRIE0 UDRIE |
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#define RXEN0 RXEN |
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#define TXEN0 TXEN |
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#define UCSZ02 UCSZ2 |
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#define RXB80 RXB8 |
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#define TXB80 TXB8 |
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/* UCSRC */ |
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#define UMSEL 6 |
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#define UPM1 5 |
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#define UPM0 4 |
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#define USBS 3 |
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#define UCSZ1 2 |
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#define UCSZ0 1 |
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#define UCPOL 0 |
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/* UCSR0C -- For compatibility with previous releases. */ |
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#define UMSEL0 UMSEL |
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#define UPM01 UPM1 |
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#define UPM00 UPM0 |
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#define USBS0 USBS |
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#define UCSZ01 UCSZ1 |
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#define UCSZ00 UCSZ0 |
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#define UCPOL0 UCPOL |
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/* LCDCRA */ |
/* LCDCRA */ |
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#define LCDEN 7 |
#define LCDEN 7 |