JIT_OP_IMIN: [=reg, imm, imm] -> { if((jit_int)$2 < (jit_int)$3) x86_mov_reg_imm(inst, $1, $2); else x86_mov_reg_imm(inst, $1, $3); } [=reg, imm, local] -> { x86_alu_membase_imm(inst, X86_CMP, X86_EBP, $3, $2); x86_mov_reg_imm(inst, $1, $2); x86_cmov_membase(inst, X86_CC_LT, 1, $1, X86_EBP, $3); } [=reg, imm, reg] -> { x86_alu_reg_imm(inst, X86_CMP, $3, $2); if($1 != $3) { x86_mov_reg_imm(inst, $1, $2); x86_cmov_reg(inst, X86_CC_LT, 1, $1, $3); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_LT, 0, 1); x86_mov_reg_imm(inst, $1, $2); x86_patch(patch, inst); } } [=reg, local, imm] -> { x86_mov_reg_imm(inst, $1, $3); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 1, $1, X86_EBP, $2); } [=reg, local, reg] -> { x86_alu_membase_reg(inst, X86_CMP, X86_EBP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_GT, 1, $1, $3); x86_cmov_membase(inst, X86_CC_LE, 1, $1, X86_EBP, $2); } [=reg, reg, imm] -> { x86_alu_reg_imm(inst, X86_CMP, $2, $3); if($1 != $2) { x86_mov_reg_imm(inst, $1, $3); x86_cmov_reg(inst, X86_CC_LT, 1, $1, $2); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_LT, 0, 1); x86_mov_reg_imm(inst, $1, $3); x86_patch(patch, inst); } } [=reg, reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, $2, X86_EBP, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); x86_cmov_membase(inst, X86_CC_LE, 1, $1, X86_EBP, $3); } [=reg, reg, reg] -> { if($2 != $3) { x86_alu_reg_reg(inst, X86_CMP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_GT, 1, $1, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_LE, 1, $1, $2); } else { if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); } } JIT_OP_IMIN_UN: [=reg, imm, imm] -> { if((jit_uint)$2 < (jit_uint)$3) x86_mov_reg_imm(inst, $1, $2); else x86_mov_reg_imm(inst, $1, $3); } [=reg, imm, local] -> { x86_alu_membase_imm(inst, X86_CMP, X86_EBP, $3, $2); x86_mov_reg_imm(inst, $1, $2); x86_cmov_membase(inst, X86_CC_LT, 0, $1, X86_EBP, $3); } [=reg, imm, reg] -> { x86_alu_reg_imm(inst, X86_CMP, $3, $2); if($1 != $3) { x86_mov_reg_imm(inst, $1, $2); x86_cmov_reg(inst, X86_CC_LT, 0, $1, $3); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_LT, 0, 0); x86_mov_reg_imm(inst, $1, $2); x86_patch(patch, inst); } } [=reg, local, imm] -> { x86_mov_reg_imm(inst, $1, $3); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 0, $1, X86_EBP, $2); } [=reg, local, reg] -> { x86_alu_membase_reg(inst, X86_CMP, X86_EBP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_GT, 0, $1, $3); x86_cmov_membase(inst, X86_CC_LE, 0, $1, X86_EBP, $2); } [=reg, reg, imm] -> { x86_alu_reg_imm(inst, X86_CMP, $2, $3); if($1 != $2) { x86_mov_reg_imm(inst, $1, $3); x86_cmov_reg(inst, X86_CC_LT, 0, $1, $2); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_LT, 0, 1); x86_mov_reg_imm(inst, $1, $3); x86_patch(patch, inst); } } [=reg, reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, $2, X86_EBP, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_GT, 0, $1, $2); x86_cmov_membase(inst, X86_CC_LE, 0, $1, X86_EBP, $3); } [=reg, reg, reg] -> { if($2 != $3) { x86_alu_reg_reg(inst, X86_CMP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_GT, 0, $1, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_LE, 0, $1, $2); } else { if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); } } JIT_OP_LMIN: binary [lreg, imm] -> { jit_uint value1 = ((jit_uint *)($2))[0]; jit_int value2 = ((jit_int *)($2))[1]; unsigned char *patch1, *patch2; x86_alu_reg_imm(inst, X86_CMP, %1, value2); patch1 = inst; x86_branch8(inst, X86_CC_GT, 0, 1); x86_alu_reg_imm(inst, X86_CMP, $1, value1); patch2 = inst; x86_branch8(inst, X86_CC_GE, 0, 0); x86_mov_reg_imm(inst, $1, value1); x86_mov_reg_imm(inst, %1, value2); x86_patch(patch1, inst); x86_patch(patch2, inst); } [lreg, local] -> { unsigned char *patch; x86_alu_reg_membase(inst, X86_CMP, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 1, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 1, $1, X86_EBP, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 1, $1, X86_EBP, $2); x86_patch(patch, inst); } [lreg, lreg] -> { if($1 != $2 && %1 != %2) { unsigned char *patch; x86_alu_reg_reg(inst, X86_CMP, %1, %2); x86_cmov_reg(inst, X86_CC_GT, 1, %1, %2); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_reg(inst, X86_CMP, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); x86_patch(patch, inst); } } JIT_OP_LMIN_UN: binary [lreg, imm] -> { jit_uint value1 = ((jit_uint *)($2))[0]; jit_int value2 = ((jit_int *)($2))[1]; unsigned char *patch1, *patch2; x86_alu_reg_imm(inst, X86_CMP, %1, value2); patch1 = inst; x86_branch8(inst, X86_CC_LT, 0, 0); x86_alu_reg_imm(inst, X86_CMP, $1, value1); patch2 = inst; x86_branch8(inst, X86_CC_LE, 0, 0); x86_mov_reg_imm(inst, $1, value1); x86_mov_reg_imm(inst, %1, value2); x86_patch(patch1, inst); x86_patch(patch2, inst); } [lreg, local] -> { unsigned char *patch; x86_alu_reg_membase(inst, X86_CMP, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 0, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 0, $1, X86_EBP, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 0); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 0, $1, X86_EBP, $2); x86_patch(patch, inst); } [lreg, lreg] -> { if($1 != $2 && %1 != %2) { unsigned char *patch; x86_alu_reg_reg(inst, X86_CMP, %1, %2); x86_cmov_reg(inst, X86_CC_GT, 0, %1, %2); x86_cmov_reg(inst, X86_CC_GT, 0, $1, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 0); x86_alu_reg_reg(inst, X86_CMP, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); x86_patch(patch, inst); } } JIT_OP_IMAX: [=reg, imm, imm] -> { if((jit_uint)$2 > (jit_uint)$3) x86_mov_reg_imm(inst, $1, $2); else x86_mov_reg_imm(inst, $1, $3); } [=reg, imm, local] -> { x86_alu_membase_imm(inst, X86_CMP, X86_EBP, $3, $2); x86_mov_reg_imm(inst, $1, $2); x86_cmov_membase(inst, X86_CC_LT, 1, $1, X86_EBP, $3); } [=reg, imm, reg] -> { x86_alu_reg_imm(inst, X86_CMP, $3, $2); if($1 != $3) { x86_mov_reg_imm(inst, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $3); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_GT, 0, 1); x86_mov_reg_imm(inst, $1, $2); x86_patch(patch, inst); } } [=reg, local, imm] -> { x86_mov_reg_imm(inst, $1, $3); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_LT, 1, $1, X86_EBP, $2); } [=reg, local, reg] -> { x86_alu_membase_reg(inst, X86_CMP, X86_EBP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_LT, 1, $1, $3); x86_cmov_membase(inst, X86_CC_GE, 1, $1, X86_EBP, $2); } [=reg, reg, imm] -> { x86_alu_reg_imm(inst, X86_CMP, $2, $3); if($1 != $2) { x86_mov_reg_imm(inst, $1, $3); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_GT, 0, 1); x86_mov_reg_imm(inst, $1, $3); x86_patch(patch, inst); } } [=reg, reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, $2, X86_EBP, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_LT, 1, $1, $2); x86_cmov_membase(inst, X86_CC_GE, 1, $1, X86_EBP, $3); } [=reg, reg, reg] -> { if($2 != $3) { x86_alu_reg_reg(inst, X86_CMP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_LT, 1, $1, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_GE, 1, $1, $2); } else { if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); } } JIT_OP_IMAX_UN: [=reg, imm, imm] -> { if((jit_uint) $2 > (jit_uint)$3) x86_mov_reg_imm(inst, $1, $2); else x86_mov_reg_imm(inst, $1, $3); } [=reg, imm, local] -> { x86_alu_membase_imm(inst, X86_CMP, X86_EBP, $3, $2); x86_mov_reg_imm(inst, $1, $2); x86_cmov_membase(inst, X86_CC_GT, 0, $1, X86_EBP, $3); } [=reg, imm, reg] -> { x86_alu_reg_imm(inst, X86_CMP, $3, $2); if($1 != $3) { x86_mov_reg_imm(inst, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 0, $1, $3); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_GT, 0, 0); x86_mov_reg_imm(inst, $1, $2); x86_patch(patch, inst); } } [=reg, local, imm] -> { x86_mov_reg_imm(inst, $1, $3); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_LT, 0, $1, X86_EBP, $2); } [=reg, local, reg] -> { x86_alu_membase_reg(inst, X86_CMP, X86_EBP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_LT, 0, $1, $3); x86_cmov_membase(inst, X86_CC_GE, 0, $1, X86_EBP, $2); } [=reg, reg, imm] -> { x86_alu_reg_imm(inst, X86_CMP, $2, $3); if($1 != $2) { x86_mov_reg_imm(inst, $1, $3); x86_cmov_reg(inst, X86_CC_GT, 0, $1, $2); } else { unsigned char *patch; patch = inst; x86_branch8(inst, X86_CC_GT, 0, 1); x86_mov_reg_imm(inst, $1, $3); x86_patch(patch, inst); } } [=reg, reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, $2, X86_EBP, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_LT, 0, $1, $2); x86_cmov_membase(inst, X86_CC_GE, 0, $1, X86_EBP, $3); } [=reg, reg, reg] -> { if($2 != $3) { x86_alu_reg_reg(inst, X86_CMP, $2, $3); if($1 != $3) x86_cmov_reg(inst, X86_CC_LT, 0, $1, $3); if($1 != $2) x86_cmov_reg(inst, X86_CC_GE, 0, $1, $2); } else { if($1 != $2) x86_mov_reg_reg(inst, $1, $2, 4); } } JIT_OP_LMAX: binary [lreg, imm] -> { jit_uint value1 = ((jit_uint *)($2))[0]; jit_int value2 = ((jit_int *)($2))[1]; unsigned char *patch1, *patch2; x86_alu_reg_imm(inst, X86_CMP, %1, value2); patch1 = inst; x86_branch8(inst, X86_CC_GT, 0, 1); x86_alu_reg_imm(inst, X86_CMP, $1, value1); patch2 = inst; x86_branch8(inst, X86_CC_GE, 0, 0); x86_mov_reg_imm(inst, $1, value1); x86_mov_reg_imm(inst, %1, value2); x86_patch(patch1, inst); x86_patch(patch2, inst); } [lreg, local] -> { unsigned char *patch; x86_alu_reg_membase(inst, X86_CMP, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 1, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 1, $1, X86_EBP, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 1, $1, X86_EBP, $2); x86_patch(patch, inst); } [lreg, lreg] -> { if($1 != $2 && %1 != %2) { unsigned char *patch; x86_alu_reg_reg(inst, X86_CMP, %1, %2); x86_cmov_reg(inst, X86_CC_LT, 1, %1, %2); x86_cmov_reg(inst, X86_CC_LT, 1, $1, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_reg(inst, X86_CMP, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 1, $1, $2); x86_patch(patch, inst); } } JIT_OP_LMAX_UN: binary [lreg, imm] -> { jit_uint value1 = ((jit_uint *)($2))[0]; jit_uint value2 = ((jit_uint *)($2))[1]; unsigned char *patch1, *patch2; x86_alu_reg_imm(inst, X86_CMP, %1, value2); patch1 = inst; x86_branch8(inst, X86_CC_GT, 0, 0); x86_alu_reg_imm(inst, X86_CMP, $1, value1); patch2 = inst; x86_branch8(inst, X86_CC_GE, 0, 0); x86_mov_reg_imm(inst, $1, value1); x86_mov_reg_imm(inst, %1, value2); x86_patch(patch1, inst); x86_patch(patch2, inst); } [lreg, local] -> { unsigned char *patch; x86_alu_reg_membase(inst, X86_CMP, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 0, %1, X86_EBP, $2 + 4); x86_cmov_membase(inst, X86_CC_LT, 0, $1, X86_EBP, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 0); x86_alu_reg_membase(inst, X86_CMP, $1, X86_EBP, $2); x86_cmov_membase(inst, X86_CC_GT, 0, $1, X86_EBP, $2); x86_patch(patch, inst); } [lreg, lreg] -> { if($1 != $2 && %1 != %2) { unsigned char *patch; x86_alu_reg_reg(inst, X86_CMP, %1, %2); x86_cmov_reg(inst, X86_CC_LT, 0, %1, %2); x86_cmov_reg(inst, X86_CC_LT, 0, $1, $2); patch = inst; x86_branch8(inst, X86_CC_NE, 0, 0); x86_alu_reg_reg(inst, X86_CMP, $1, $2); x86_cmov_reg(inst, X86_CC_GT, 0, $1, $2); x86_patch(patch, inst); } } JIT_OP_ISIGN: [=reg, imm] -> { if($2 < 0) x86_mov_reg_imm(inst, $1, -1); else x86_mov_reg_imm(inst, $1, 0); } [=reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, X86_EBP, $2, 0); x86_set_reg(inst, X86_CC_LT, $1, 1); x86_widen_reg(inst, $1, $1, 0, 0); x86_neg_reg(inst, $1); } [=reg, reg] -> { x86_alu_reg_imm(inst, X86_CMP, $2, 0); x86_set_reg(inst, X86_CC_LT, $1, 1); x86_widen_reg(inst, $1, $1, 0, 0); x86_neg_reg(inst, $1); } JIT_OP_LSIGN: [=reg, lreg, imm] -> { jit_uint value1 = ((jit_uint *)($3))[0]; jit_int value2 = ((jit_int *)($3))[1]; unsigned char *patch1, *patch2; x86_alu_reg_imm(inst, X86_CMP, %2, value2); patch1 = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_imm(inst, X86_CMP, $2, value1); inst = setcc_reg(inst, $1, X86_CC_GE, 0); patch2 = inst; x86_jump8(inst, 0); x86_patch(patch1, inst); inst = setcc_reg(inst, $1, X86_CC_GE, 1); x86_patch(patch2, inst); } [=reg, lreg, local] -> { unsigned char *patch1, *patch2; x86_alu_reg_membase(inst, X86_CMP, %2, X86_EBP, $3 + 4); patch1 = inst; x86_branch8(inst, X86_CC_NE, 0, 1); x86_alu_reg_membase(inst, X86_CMP, $2, X86_EBP, $3); inst = setcc_reg(inst, $1, X86_CC_GE, 0); patch2 = inst; x86_jump8(inst, 0); x86_patch(patch1, inst); inst = setcc_reg(inst, $1, X86_CC_GE, 1); x86_patch(patch2, inst); } [=reg, imm] -> { jit_long value = ((jit_long*)($2))[0]; if(value < 0) x86_mov_reg_imm(inst, $1, -1); else x86_mov_reg_imm(inst, $1, 0); } [=reg, local] -> { x86_alu_reg_membase(inst, X86_CMP, X86_EBP, $2 + 4, 0); x86_set_reg(inst, X86_CC_LT, $1, 1); x86_widen_reg(inst, $1, $1, 0, 0); x86_neg_reg(inst, $1); } [=reg, lreg] -> { x86_alu_reg_imm(inst, X86_CMP, %2, 0); x86_set_reg(inst, X86_CC_LT, $1, 1); x86_widen_reg(inst, $1, $1, 0, 0); x86_neg_reg(inst, $1); }