/* * jit-gen-i486-simd.h: Macros for generating Streaming SIMD Extensions code. * * Copyright (C) 2007 Free Software Foundation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 3 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef JIT_GEN_SSE_H #define JIT_GEN_SSE_H #include /* // The XMM register numbers, for P3 and up chips */ typedef enum { XMM0 = 0, XMM1 = 1, XMM2 = 2, XMM3 = 3, XMM4 = 4, XMM5 = 5, XMM6 = 6, XMM7 = 7, XMM_NREG } XMM_Reg_No; /* // The MMX register numbers, for P3 and up chips */ typedef enum { MM0 = 0, MM1 = 1, MM2 = 2, MM3 = 3, MM4 = 4, MM5 = 5, MM6 = 6, MM7 = 7, MM_NREG } MMX_Reg_No; #define emit_mmx_operand_reg_reg(inst,dreg,reg) \ do { \ x86_reg_emit((inst), (dreg), (reg)); \ } while(0) #define emit_mmx_operand_reg_mem(inst,reg,mem) \ do { \ x86_mem_emit((inst), (reg), (mem)); \ } while(0) #define emit_mmx_operand_reg_membase(inst,reg,basereg,disp) \ do { \ x86_membase_emit((inst), (reg), (basereg), (disp)); \ } while(0) /* * The MMX instruction set is higly regular, so this macro saves * a lot of cut&paste */ #define emit_mmx_instruction_reg_reg(inst,opcode,dreg,reg) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_mmx_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define emit_mmx_instruction_reg_mem(inst,opcode,dreg,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define emit_mmx_instruction_reg_membase(inst,opcode,dreg,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define mmx_por_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xeb), (dreg), (reg)); \ } while (0) #define mmx_por_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xeb), (dreg), (mem)); \ } while(0) #define mmx_por_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xeb), (dreg), (basereg), (disp)); \ } while(0) #define mmx_psadbw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xf6), (dreg), (reg)); \ } while(0) #define mmx_psadbw_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xf6), (dreg), (mem)); \ } while(0) #define mmx_psadbw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xf6), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pshufw_mmreg_mmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x70), (dreg), (reg)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define mmx_pshufw_mmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x70), (dreg), (mem)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define mmx_pshufw_mmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x70), (dreg), (basereg), (disp)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define sse2_paddq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xd4), (dreg), (reg)); \ } while(0) #define sse2_paddq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xd4), (dreg), (mem)); \ } while(0) #define sse2_paddq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xd4), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xfb), (dreg), (reg)); \ } while(0) #define sse2_psubq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xfb), (dreg), (mem)); \ } while(0) #define sse2_psubq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xfb), (dreg), (basereg), (disp)); \ } while(0) #define mmx_movd_mmreg_reg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x6e), (dreg), (reg)); \ } while(0) #define mmx_movd_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x6e), (dreg), (mem)); \ } while(0) #define mmx_movd_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x6e), (dreg), (basereg), (disp)); \ } while(0) #define mmx_movd_reg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x7e), (reg), (dreg)); \ } while(0) #define mmx_movd_membase_mmreg(inst,basereg,disp,reg) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x7e), (reg), (basereg), (disp)); \ } while(0) #define mmx_movd_mem_mmreg(inst,mem,reg) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x7e), (reg), (mem)); \ } while(0) #define mmx_movq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x6f), (dreg), (reg)); \ } while(0) #define mmx_movq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x6f), (dreg), (mem)); \ } while(0) #define mmx_movq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x6f), (dreg), (basereg), (disp)); \ } while(0) #define mmx_movq_mem_mmreg(inst,mem,dreg) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x7f), (dreg), (mem)); \ } while(0) #define mmx_movq_membase_mmreg(inst,basereg,disp,dreg) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x7f), (dreg), (basereg), (disp)); \ } while(0) #define mmx_movntq_mem_mmreg(inst,mem,dreg) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xe7), (dreg), (mem)); \ } while(0) #define mmx_movntq_membase_mmreg(inst,basereg,disp,dreg) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xe7), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pand_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xdb), (dreg), (reg)); \ } while(0) #define mmx_pand_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xdb), (dreg), (mem)); \ } while(0) #define mmx_pand_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xdb), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pandn_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xdf), (dreg), (reg)); \ } while(0) #define mmx_pandn_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xdf), (dreg), (mem)); \ } while(0) #define mmx_pandn_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xdf), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pxor_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0xef), (dreg), (reg)); \ } while(0) #define mmx_pxor_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0xef), (dreg), (mem)); \ } while(0) #define mmx_pxor_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0xef), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpeqb_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x74), (dreg), (reg)); \ } while(0) #define mmx_pcmpeqb_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x74), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpeqb_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x74), (dreg), (mem)); \ } while(0) #define mmx_pcmpeqw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x75), (dreg), (reg)); \ } while(0) #define mmx_pcmpeqw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x75), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpeqd_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x76), (dreg), (reg)); \ } while(0) #define mmx_pcmpeqd_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x76), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpeqd_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x76), (dreg), (mem)); \ } while(0) #define mmx_pcmpgtb_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x64), (dreg), (reg)); \ } while(0) #define mmx_pcmpgtb_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x64), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpgtb_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x64), (dreg), (mem)); \ } while(0) #define mmx_pcmpgtw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x65), (dreg), (reg)); \ } while(0) #define mmx_pcmpgtw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x65), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpgtw_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x65), (dreg), (mem)); \ } while(0) #define mmx_pcmpgtd_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg((inst), (0x66), (dreg), (reg)); \ } while(0) #define mmx_pcmpgtd_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase((inst), (0x66), (dreg), (basereg), (disp)); \ } while(0) #define mmx_pcmpgtd_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem((inst), (0x66), (dreg), (mem)); \ } while(0) #define mmx_psllw_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_mmx_operand_reg_membase((inst), (dreg), (reg)); \ } while(0) #define mmx_psllw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define mmx_psllw_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_psllw_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_mmx_operand_reg_reg((inst), (MM6), (dreg)); \ *(inst) ++ = (unsigned char)((int)(shift) & 0xff); \ } while(0) #define mmx_pslld_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_mmx_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define mmx_pslld_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg),(disp)); \ } while(0) #define mmx_pslld_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_pslld_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_mmx_operand_reg_reg((inst), (MM6), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define mmx_psllq_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_mmx_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define mmx_psllq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define mmx_psllq_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_psllq_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_mmx_operand_reg_reg((inst), (MM6), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define mmx_psrlw_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_mmx_operand_reg_membase((inst), (dreg), (reg)); \ } while(0) #define mmx_psrlw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define mmx_psrlw_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_psrlw_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_mmx_operand_reg_reg((inst), (MM2), (dreg)); \ *(inst) ++ = (unsigned char)((int)(shift) & 0xff); \ } while(0) #define mmx_psrld_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_mmx_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define mmx_psrld_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg),(disp)); \ } while(0) #define mmx_psrld_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_psrld_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_mmx_operand_reg_reg((inst), (MM2), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define mmx_psrlq_mmreg_mmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_mmx_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define mmx_psrlq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_mmx_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define mmx_psrlq_mmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_mmx_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define mmx_psrlq_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_mmx_operand_reg_reg((inst), (MM2), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define mmx_punpckhbw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x68), (dreg), (reg)); \ } while(0) #define mmx_punpckhbw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x68), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpckhbw_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x68), (dreg), (mem)); \ } while(0) #define mmx_punpckhwd_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x69), (dreg), (reg)); \ } while(0) #define mmx_punpckhwd_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x69), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpckhwd_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x69), (dreg), (mem)); \ } while(0) #define mmx_punpckhdq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x6a), (dreg), (reg)); \ } while(0) #define mmx_punpckhdq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x6a), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpckhdq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x6a), (dreg), (mem)); \ } while(0) #define mmx_punpcklbw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x60), (dreg), (reg)); \ } while(0) #define mmx_punpcklbw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x60), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpcklbw_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x60), (dreg), (mem)); \ } while(0) #define mmx_punpcklwd_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x61), (dreg), (reg)); \ } while(0) #define mmx_punpcklwd_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x61), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpcklwd_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x61), (dreg), (mem)); \ } while(0) #define mmx_punpckldq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x62), (dreg), (reg)); \ } while(0) #define mmx_punpckldq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x62), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpckldq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x62), (dreg), (mem)); \ } while(0) #define mmx_punpcklqdq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_mmx_instruction_reg_reg(inst, (0x6C), (dreg), (reg)); \ } while(0) #define mmx_punpcklqdq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_mmx_instruction_reg_membase(inst, (0x6C), (dreg), (basereg), (disp)); \ } while(0) #define mmx_punpcklqdq_mmreg_mem(inst,dreg,mem) \ do { \ emit_mmx_instruction_reg_mem(inst, (0x6C), (dreg), (mem)); \ } while(0) #define mmx_emms(inst) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x77; \ } while(0) // Pseudo instruction for 'push' of MMX registers. #define mmx_push_mmreg(inst,dreg) \ do { \ x86_alu_reg_imm(inst, X86_SUB, X86_ESP, 8); \ mmx_movq_membase_mmreg(inst, X86_ESP, 0, (dreg)); \ } while(0) /* * SSE, 3DNow!, SSE2, SSE3 and SSE4 instruction set */ #define sse_prefetcht0_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_mem_emit((inst), (X86_ECX), (mem)); \ } while(0) #define sse_prefetcht0_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_membase_emit((inst), (X86_ECX), (basereg), (disp)); \ } while(0) #define sse_prefetcht1_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_mem_emit((inst), (X86_EDX), (mem)); \ } while(0) #define sse_prefetcht1_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_membase_emit((inst), (X86_EDX), (basereg), (disp)); \ } while(0) #define sse_prefetcht2_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_mem_emit((inst), (X86_EBX), (mem)); \ } while(0) #define sse_prefetcht2_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_membase_emit((inst), (X86_EBX), (basereg), (disp)); \ } while(0) #define sse_prefetchnta_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_mem_emit((inst), (X86_EAX), (mem)); \ } while(0) #define sse_prefetchnta_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x18; \ x86_membase_emit((inst), (X86_EAX), (basereg), (disp)); \ } while(0) #define mmx_sfence(inst) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0xae; \ x86_reg_emit((inst), 7, 0); \ } while(0) #define _3dnow_prefetchw_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x0D; \ x86_mem_emit((inst), (X86_ECX), (mem)); \ } while(0) #define _3dnow_prefetchw_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x0D; \ x86_membase_emit((inst), (X86_ECX), (basereg), (disp)); \ } while(0) #define _3dnow_prefetchr_mem(inst,mem) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x0D; \ x86_mem_emit((inst), (X86_EAX), (mem)); \ } while(0) #define _3dnow_prefetchr_membase(inst,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x0D; \ x86_membase_emit((inst), (X86_EAX), (basereg), (disp)); \ } while(0) #define emit_sse_operand_reg_reg(inst,dreg,reg) \ do { \ x86_reg_emit((inst), (dreg), (reg)); \ } while(0) #define emit_sse_operand_reg_mem(inst,reg,mem) \ do { \ x86_mem_emit((inst), (reg), (mem)); \ } while(0) #define emit_sse_operand_reg_membase(inst,reg,basereg,disp) \ do { \ x86_membase_emit((inst), (reg), (basereg), (disp)); \ } while(0) /* * The SSE instruction set is highly regular, so this macro saves * a lot of cut&paste * * Macro parameters: * * prefix: first opcode byte of the intsruction (or 0 if no prefix byte) * * opcode: last opcode byte of the instruction * * dreg: either a GP or a XMM destination register * * reg: either a GP or a XMM source register */ #define emit_sse_instruction_reg_reg(inst,prefix,opcode,dreg,reg) \ do { \ if (prefix != 0) *(inst)++ = (unsigned char)prefix; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define emit_sse_instruction_reg_mem(inst,prefix,opcode,dreg,mem) \ do { \ if (prefix != 0) *(inst)++ = (unsigned char)prefix; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define emit_sse_instruction_reg_membase(inst,prefix,opcode,dreg,basereg,disp) \ do { \ if (prefix != 0) *(inst)++ = (unsigned char)prefix; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)opcode; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define emit_sse4_instruction_reg_reg(inst,opcode,dreg,reg) \ do { \ *(inst)++ = (unsigned char)0x66; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x38; \ *(inst)++ = (unsigned char)opcode; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define emit_sse4_instruction_reg_mem(inst,opcode,dreg,mem) \ do { \ *(inst)++ = (unsigned char)0x66; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x38; \ *(inst)++ = (unsigned char)opcode; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define emit_sse4_instruction_reg_membase(inst,opcode,dreg,basereg,disp) \ do { \ *(inst)++ = (unsigned char)0x66; \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x38; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_addpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x58), (dreg), (reg)); \ } while(0) #define sse2_addpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x58), (dreg), (basereg), (disp)); \ } while(0) #define sse2_addpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x58), (dreg), (mem)); \ } while(0) #define sse_addss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x58), (dreg), (reg)); \ } while(0) #define sse_addss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf3), (0x58), (dreg), (basereg), (disp)); \ } while(0) #define sse_addss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf3), (0x58), (dreg), (mem)); \ } while(0) #define sse3_addsusbpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xd0), (dreg), (reg)); \ } while(0) #define sse3_addsusbpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xd0), (dreg), (basereg), (disp)); \ } while(0) #define sse3_addsusbpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xd0), (dreg), (mem)); \ } while(0) #define sse3_addsusbps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0xd0), (dreg), (reg)); \ } while(0) #define sse3_addsusbps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf2), (0xd0), (dreg), (basereg), (disp)); \ } while(0) #define sse3_addsusbps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf2), (0xd0), (dreg), (mem)); \ } while(0) #define sse2_addsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x58), (dreg), (reg)); \ } while(0) #define sse2_addsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf2), (0x58), (dreg), (basereg), (disp)); \ } while(0) #define sse2_addsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf2), (0x58), (dreg), (mem)); \ } while(0) #define sse_andps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x0), (0x54), (dreg), (reg)); \ } while(0) #define sse_andps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x54), (dreg), (basereg), (disp)); \ } while(0) #define sse_andps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x54), (dreg), (mem)); \ } while(0) #define sse2_andpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x66), (0x54), (dreg), (reg)); \ } while(0) #define sse2_andpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x54), (dreg), (basereg), (disp)); \ } while(0) #define sse2_andpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x54), (dreg), (mem)); \ } while(0) #define sse_andnps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x0), (0x55), (dreg), (reg)); \ } while(0) #define sse_andnps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x55), (dreg), (basereg), (disp)); \ } while(0) #define sse_andnps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x55), (dreg), (mem)); \ } while(0) #define sse2_andnpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x66), (0x55), (dreg), (reg)); \ } while(0) #define sse2_andnpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x55), (dreg), (basereg), (disp)); \ } while(0) #define sse2_andnpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x55), (dreg), (mem)); \ } while(0) #define sse2_cmppd_xmreg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xc2), (dreg), (reg)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmppd_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xc2), (dreg), (basereg),(disp)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmppd_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xc2), (dreg), (mem)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmpeqpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(0)); \ } while(0) #define sse2_cmpeqpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ sse2_cmppd_xmreg_membase_imm8((inst),(dreg),(basereg),(disp),(0)); \ } while(0) #define sse2_cmpeqpd_xmreg_mem(inst,dreg,mem) \ do { \ sse2_cmppd_xmreg_mem_imm8((inst),(dreg),(mem),(0)); \ } while(0) #define sse2_cmpltpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(1)); \ } while(0) #define sse2_cmplepd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(2)); \ } while(0) #define sse2_cmpunordpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(3)); \ } while(0) #define sse2_cmpneqpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(4)); \ } while(0) #define sse2_cmpnltpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(5)); \ } while(0) #define sse2_cmpnlepd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(6)); \ } while(0) #define sse2_cmpordpd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmppd_xmreg_xmreg_imm8((inst),(dreg),(reg),(7)); \ } while(0) #define sse_cmpps_xmreg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction((inst), (0x0), (0xc2), (dreg), (reg)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse_cmpps_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0xc2), (dreg), (basereg),(disp)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse_cmpps_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0xc2), (dreg), (mem)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse_cmpeqps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(0)); \ } while(0) #define sse_cmpltps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(1)); \ } while(0) #define sse_cmpleps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(2)); \ } while(0) #define sse_cmpunordps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(3)); \ } while(0) #define sse_cmpneqps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(4)); \ } while(0) #define sse_cmpnltps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(5)); \ } while(0) #define sse_cmpnleps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(6)); \ } while(0) #define sse_cmpordps_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpps_xmreg_xmreg_imm8((inst),(dreg),(reg),(7)); \ } while(0) #define sse2_cmpsd_xmreg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0xc2), (dreg), (reg)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmpsd_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0xc2), (dreg), (basereg),(disp)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmpsd_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0xc2), (dreg), (mem)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse2_cmpeqsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(0)); \ } while(0) #define sse2_cmpltsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(1)); \ } while(0) #define sse2_cmplesd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(2)); \ } while(0) #define sse2_cmpunordsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(3)); \ } while(0) #define sse2_cmpneqsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(4)); \ } while(0) #define sse2_cmpnltsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(5)); \ } while(0) #define sse2_cmpnlesd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(6)); \ } while(0) #define sse2_cmpordsd_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpsd_xmreg_xmreg_imm8((inst),(dreg),(reg),(7)); \ } while(0) #define sse_cmpss_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0xc2), (dreg), (basereg),(disp)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse_cmpss_xmreg_mem_imm8(inst,dreg,memm,imm) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0xc2), (dreg), (mem)); \ *(inst)++ = (unsigned char)(int)((imm) & 0xf); \ } while(0) #define sse_cmpeqss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(0)); \ } while(0) #define sse_cmpltss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(1)); \ } while(0) #define sse_cmpless_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(2)); \ } while(0) #define sse_cmpunordss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(3)); \ } while(0) #define sse_cmpneqss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(4)); \ } while(0) #define sse_cmpnltss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(5)); \ } while(0) #define sse_cmpnless_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(6)); \ } while(0) #define sse_cmpordss_xmreg_xmreg(inst,dreg,reg) \ do { \ sse2_cmpss_xmreg_xmreg_imm8((inst),(dreg),(reg),(7)); \ } while(0) #define sse_comiss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x2f), (dreg), (reg)); \ } while(0) #define sse_comiss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x2f), (dreg), (basereg), (disp)); \ } while(0) #define sse_comiss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x2f), (dreg), (mem)); \ } while(0) #define sse2_comisd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2f), (dreg), (reg)); \ } while(0) #define sse2_comisd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x2f), (dreg), (basereg), (disp)); \ } while(0) #define sse2_comisd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x2f), (dreg), (mem)); \ } while(0) #define sse2_cvtdq2pd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0xe6), (dreg), (reg)); \ } while(0) #define sse2_cvtdq2pd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0xe6), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtdq2pd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0xe6), (dreg), (mem)); \ } while(0) #define sse_cvtdq2ps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5b), (dreg), (reg)); \ } while(0) #define sse_cvtdq2ps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x5b), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtdq2ps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x5b), (dreg), (mem)); \ } while(0) #define sse2_cvtpd2dq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0xe6), (dreg), (reg)); \ } while(0) #define sse2_cvtpd2dq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0xe6), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtpd2dq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0xe6), (dreg), (mem)); \ } while(0) #define sse2_cvtpd2pi_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2d), (dreg), (reg)); \ } while(0) #define sse2_cvtpd2pi_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x2d), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtpd2pi_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x2d), (dreg), (mem)); \ } while(0) #define sse_cvtpd2ps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5a), (dreg), (reg)); \ } while(0) #define sse_cvtpd2ps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x5a), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtpd2ps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x5a), (dreg), (mem)); \ } while(0) #define sse2_cvtpi2pd_xmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2a), (dreg), (reg)); \ } while(0) #define sse2_cvtpi2pd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x2a), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtpi2pd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x2a), (dreg), (mem)); \ } while(0) #define sse_cvtpi2ps_xmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x2a), (dreg), (reg)); \ } while(0) #define sse_cvtpi2ps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x2a), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtpi2ps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x2a), (dreg), (mem)); \ } while(0) #define sse2_cvtps2dq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5b), (dreg), (reg)); \ } while(0) #define sse2_cvtps2dq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x5b), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtps2dq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x5b), (dreg), (mem)); \ } while(0) #define sse2_cvtps2pd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5a), (dreg), (reg)); \ } while(0) #define sse2_cvtps2pd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x5a), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtps2pd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x5a), (dreg), (mem)); \ } while(0) #define sse_cvtps2pi_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x2d), (dreg), (reg)); \ } while(0) #define sse_cvtps2pi_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x2d), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtps2pi_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x2d), (dreg), (mem)); \ } while(0) #define sse_cvtsd2si_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x2d), (dreg), (reg)); \ } while(0) #define sse_cvtsd2si_reg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x2d), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtsd2si_reg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x2d), (dreg), (mem)); \ } while(0) #define sse_cvtsd2ss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x5a), (dreg), (reg)); \ } while(0) #define sse_cvtsd2ss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x5a), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtsd2ss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x5a), (dreg), (mem)); \ } while(0) #define sse2_cvtsi2sd_xmreg_reg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x2a), (dreg), (reg)); \ } while(0) #define sse2_cvtsi2sd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x2a), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtsi2sd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x2a), (dreg), (mem)); \ } while(0) #define sse_cvtsi2ss_xmreg_reg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x2a), (dreg), (reg)); \ } while(0) #define sse_cvtsi2ss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x2a), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtsi2ss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x2a), (dreg), (mem)); \ } while(0) #define sse2_cvtss2sd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5a), (dreg), (reg)); \ } while(0) #define sse2_cvtss2sd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x5a), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvtss2sd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x5a), (dreg), (mem)); \ } while(0) #define sse_cvtss2si_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x2d), (dreg), (reg)); \ } while(0) #define sse_cvtss2si_reg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x2d), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvtss2si_reg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x2d), (dreg), (mem)); \ } while(0) #define sse2_cvttpd2pi_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2c), (dreg), (reg)); \ } while(0) #define sse2_cvttpd2pi_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x2c), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvttpd2pi_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x2c), (dreg), (mem)); \ } while(0) #define sse2_cvttpd2dq_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe6), (dreg), (reg)); \ } while(0) #define sse2_cvttpd2dq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe6), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvttpd2dq_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe6), (dreg), (mem)); \ } while(0) #define sse2_cvttps2dq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5b), (dreg), (reg)); \ } while(0) #define sse2_cvttps2dq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x5b), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvttps2dq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x5b), (dreg), (mem)); \ } while(0) #define sse_cvttps2pi_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x2c), (dreg), (reg)); \ } while(0) #define sse_cvttps2pi_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x2c), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvttps2pi_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x2c), (dreg), (mem)); \ } while(0) #define sse2_cvttsd2si_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x2c), (dreg), (reg)); \ } while(0) #define sse2_cvttsd2si_reg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x2c), (dreg), (basereg), (disp)); \ } while(0) #define sse2_cvttsd2si_reg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x2c), (dreg), (mem)); \ } while(0) #define sse_cvttss2si_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x2c), (dreg), (reg)); \ } while(0) #define sse_cvttss2si_reg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x2c), (dreg), (basereg), (disp)); \ } while(0) #define sse_cvttss2si_reg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x2c), (dreg), (mem)); \ } while(0) #define sse2_divpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5e), (dreg), (reg)); \ } while(0) #define sse2_divpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x5e), (dreg), (basereg), (disp)); \ } while(0) #define sse2_divpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x5e), (dreg), (mem)); \ } while(0) #define sse_divps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5e), (dreg), (reg)); \ } while(0) #define sse_divps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x5e), (dreg), (basereg), (disp)); \ } while(0) #define sse_divps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x5e), (dreg), (mem)); \ } while(0) #define sse2_divsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x5e), (dreg), (reg)); \ } while(0) #define sse2_divsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x5e), (dreg), (basereg), (disp)); \ } while(0) #define sse2_divsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x5e), (dreg), (mem)); \ } while(0) #define sse_divss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5e), (dreg), (reg)); \ } while(0) #define sse_divss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x5e), (dreg), (basereg), (disp)); \ } while(0) #define sse_divss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x5e), (dreg), (mem)); \ } while(0) #define sse_fxrstor_mem(inst,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_mem((inst), (X86_ECX), (mem)); \ } while(0) #define sse_fxrstor_membase(inst,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_membase((inst), (X86_ECX), (basereg), (disp)); \ } while(0) #define sse_fxsave_mem(inst,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_mem((inst), (X86_EAX), (mem)); \ } while(0) #define sse_fxsave_membase(inst,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_membase((inst), (X86_EAX), (basereg), (disp)); \ } while(0) #define sse3_haddpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x7c), (dreg), (reg)); \ } while(0) #define sse3_haddpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x7c), (dreg), (basereg), (disp)); \ } while(0) #define sse3_haddpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x7c), (dreg), (mem)); \ } while(0) #define sse3_haddps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x7c), (dreg), (reg)); \ } while(0) #define sse3_haddps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x7c), (dreg), (basereg), (disp)); \ } while(0) #define sse3_haddps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x7c), (dreg), (mem)); \ } while(0) #define sse3_hsubpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x7d), (dreg), (reg)); \ } while(0) #define sse3_hsubpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x7d), (dreg), (basereg), (disp)); \ } while(0) #define sse3_hsubpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x7d), (dreg), (mem)); \ } while(0) #define sse3_hsubps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x7d), (dreg), (reg)); \ } while(0) #define sse3_hsubps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x7d), (dreg), (basereg), (disp)); \ } while(0) #define sse3_hsubps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x7d), (dreg), (mem)); \ } while(0) #define sse3_lddqu_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0xf0), (dreg), (basereg), (disp)); \ } while(0) #define sse3_lddqu_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0xf0), (dreg), (mem)); \ } while(0) #define sse_ldmxcsr_mem(inst,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_mem((inst), (X86_EDX), (mem)); \ } while(0) #define sse_ldmxcsr_membase(inst,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_membase((inst), (X86_EDX), (basereg), (disp)); \ } while(0) #define sse2_maskmovdqu_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xf7), (dreg), (reg)); \ } while(0) #define sse2_maxpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5f), (dreg), (reg)); \ } while(0) #define sse2_maxpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x5f), (dreg), (basereg), (disp)); \ } while(0) #define sse2_maxpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x5f), (dreg), (mem)); \ } while(0) #define sse_maxps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5f), (dreg), (reg)); \ } while(0) #define sse_maxps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x5f), (dreg), (basereg), (disp)); \ } while(0) #define sse_maxps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x5f), (dreg), (mem)); \ } while(0) #define sse2_maxsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x5f), (dreg), (reg)); \ } while(0) #define sse2_maxsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x5f), (dreg), (basereg), (disp)); \ } while(0) #define sse2_maxsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x5f), (dreg), (mem)); \ } while(0) #define sse_maxss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5f), (dreg), (reg)); \ } while(0) #define sse_maxss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x5f), (dreg), (basereg), (disp)); \ } while(0) #define sse_maxss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x5f), (dreg), (mem)); \ } while(0) #define sse2_minpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5d), (dreg), (reg)); \ } while(0) #define sse2_minpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x5d), (dreg), (basereg), (disp)); \ } while(0) #define sse2_minpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x5d), (dreg), (mem)); \ } while(0) #define sse_minps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5d), (dreg), (reg)); \ } while(0) #define sse_minps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x5d), (dreg), (basereg), (disp)); \ } while(0) #define sse_minps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x5d), (dreg), (mem)); \ } while(0) #define sse2_minsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x5d), (dreg), (reg)); \ } while(0) #define sse2_minsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x5d), (dreg), (basereg), (disp)); \ } while(0) #define sse2_minsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x5d), (dreg), (mem)); \ } while(0) #define sse_minss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5d), (dreg), (reg)); \ } while(0) #define sse_minss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x5d), (dreg), (basereg), (disp)); \ } while(0) #define sse_minss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x5d), (dreg), (mem)); \ } while(0) #define sse3_monitor(inst) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x01; \ *(inst)++ = (unsigned char)0xc8; \ } while(0) #define sse2_movapd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x28), (dreg), (reg)); \ } while(0) #define sse2_movapd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x28), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movapd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x28), (dreg), (mem)); \ } while(0) #define sse2_movapd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x29), (reg), (basereg), (disp)); \ } while(0) #define sse2_movapd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x29), (reg), (mem)); \ } while(0) #define sse_movaps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x28), (dreg), (reg)); \ } while(0) #define sse_movaps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x28), (dreg), (basereg), (disp)); \ } while(0) #define sse_movaps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x28), (dreg), (mem)); \ } while(0) #define sse_movaps_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x29), (reg), (basereg), (disp)); \ } while(0) #define sse_movaps_mem_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x29), (reg), (mem)); \ } while(0) #define sse2_movd_xmreg_reg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x6e), (dreg), (reg)); \ } while(0) #define sse2_movd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x6e), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x6e), (dreg), (mem)); \ } while(0) #define sse2_movd_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x7e), (reg), (dreg)); \ } while(0) #define sse2_movd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x7e), (reg), (basereg), (disp)); \ } while(0) #define sse2_movd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x7e), (reg), (mem)); \ } while(0) #define sse3_movddup_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x12), (dreg), (dreg)); \ } while(0) #define sse3_movddup_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x12), (dreg), (basereg), (disp)); \ } while(0) #define sse3_movddup_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x12), (dreg), (mem)); \ } while(0) #define sse2_movdqa_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x6f), (dreg), (reg)); \ } while(0) #define sse2_movdqa_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x6f), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movdqa_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x6f), (dreg), (mem)); \ } while(0) #define sse2_movdqa_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x7f), (reg), (basereg), (disp)); \ } while(0) #define sse2_movdqa_mem_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x7f), (reg), (mem)); \ } while(0) #define sse2_movdqu_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x6f), (dreg), (reg)); \ } while(0) #define sse2_movdqu_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x6f), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movdqu_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x6f), (dreg), (mem); \ } while(0) #define sse2_movdqu_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x7f), (reg), (basereg), (disp)); \ } while(0) #define sse2_movdqu_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x7f), (reg), (mem)); \ } while(0) #define sse2_movdq2q_mmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0xd6), (dreg), (reg)); \ } while(0) #define sse_movhlps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x12), (dreg), (reg)); \ } while(0) #define sse2_movhpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x16), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movhpd_xmreg_mem(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x16), (dreg), (mem)); \ } while(0) #define sse2_movhpd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x17), (reg), (basereg), (disp)); \ } while(0) #define sse2_movhpd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x17), (reg), (mem)); \ } while(0) #define sse_movhps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x16), (dreg), (basereg), (disp)); \ } while(0) #define sse_movhps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x16), (dreg), (mem)); \ } while(0) #define sse_movhps_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x17), (reg), (basereg), (disp)); \ } while(0) #define sse_movhps_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x17), (reg), (mem)); \ } while(0) #define sse_movlhps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x16), (dreg), (reg)); \ } while(0) #define sse2_movlpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x12), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movlpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x12), (dreg), (mem)); \ } while(0) #define sse2_movlpd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x13), (reg), (basereg), (disp)); \ } while(0) #define sse2_movlpd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x13), (reg), (mem)); \ } while(0) #define sse_movlps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x12), (dreg), (basereg), (disp)); \ } while(0) #define sse_movlps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x12), (dreg), (mem)); \ } while(0) #define sse_movlps_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x13), (reg), (basereg), (disp)); \ } while(0) #define sse_movlps_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x13), (reg), (mem)); \ } while(0) #define sse2_movmskpd_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x50), (dreg), (reg)); \ } while(0) #define sse_movmskps_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x50), (dreg), (reg)); \ } while(0) #define sse2_movntdq_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe7), (reg), (basereg), (disp)); \ } while(0) #define sse2_movntdq_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe7), (reg), (mem)); \ } while(0) #define sse2_movnti_membase_reg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_basereg((inst), (0x0), (0xc3), (reg), (basereg), (disp)); \ } while(0) #define sse2_movnti_mem_reg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0xc3), (reg), (mem)); \ } while(0) #define sse2_movntpd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2b), (reg), (basereg), (disp)); \ } while(0) #define sse2_movntpd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2b), (reg), (mem)); \ } while(0) #define sse_movntps_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x2b), (reg), (basereg), (disp)); \ } while(0) #define sse_movntps_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x2b), (reg), (mem)); \ } while(0) #define sse3_movshdup_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x16), (dreg), (reg)); \ } while(0) #define sse3_movshdup_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x16), (dreg), (basereg), (disp)); \ } while(0) #define sse3_movshdup_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x16), (dreg), (mem)); \ } while(0) #define sse3_movsldup_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x12), (dreg), (reg)); \ } while(0) #define sse3_movsldup_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x12), (dreg), (basereg), (disp)); \ } while(0) #define sse3_movsldup_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x12), (dreg), (mem)); \ } while(0) #define sse2_movq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x7e), (dreg), (reg)); \ } while(0) #define sse2_movq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x7e), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x7e), (dreg), (mem)); \ } while(0) #define sse2_movq_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xd6), (reg), (basereg), (disp)); \ } while(0) #define sse2_movq_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xd6), (reg), (mem)); \ } while(0) #define sse2_movq2dq_xmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0xd6), (dreg), (reg)); \ } while(0) #define sse2_movsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x10), (dreg), (reg)); \ } while(0) #define sse2_movsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x10), (dreg), (basereg), (disp)); \ } while(0) #define sse2_movsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x10), (dreg), (mem)); \ } while(0) #define sse2_movsd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x11), (reg), (basereg), (disp)); \ } while(0) #define sse2_movsd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x11), (reg), (mem)); \ } while(0) #define sse_movss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x10), (dreg), (reg)); \ } while(0) #define sse_movss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x10), (dreg), (basereg), (disp)); \ } while(0) #define sse_movss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x10), (dreg), (mem)); \ } while(0) #define sse_movss_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x11), (reg), (basereg), (disp)); \ } while(0) #define sse_movss_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x11), (reg), (mem)); \ } while(0) #define sse_movupd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x10), (dreg), (reg)); \ } while(0) #define sse_movupd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x10), (dreg), (basereg), (disp)); \ } while(0) #define sse_movupd_xmreg_mem(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x10), (dreg), (mem)); \ } while(0) #define sse_movupd_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x11), (reg), (basereg), (disp)); \ } while(0) #define sse_movupd_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x11), (reg), (mem)); \ } while(0) #define sse_movups_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x10), (dreg), (reg)); \ } while(0) #define sse_movups_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x10), (dreg), (basereg), (disp)); \ } while(0) #define sse_movups_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x10), (dreg), (mem)); \ } while(0) #define sse_movups_membase_xmreg(inst,basereg,disp,reg) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x11), (reg), (basereg), (disp)); \ } while(0) #define sse_movups_mem_xmreg(inst,mem,reg) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x11), (reg), (mem)); \ } while(0) #define sse2_mulpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x59), (dreg), (reg)); \ } while(0) #define sse2_mulpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x59), (dreg), (basereg), (disp)); \ } while(0) #define sse2_mulpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x59), (dreg), (mem)); \ } while(0) #define sse_mulps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x59), (dreg), (reg)); \ } while(0) #define sse_mulps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x59), (dreg), (basereg), (disp)); \ } while(0) #define sse_mulps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x59), (dreg), (mem)); \ } while(0) #define sse2_mulsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x59), (dreg), (reg)); \ } while(0) #define sse2_mulsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf2), (0x59), (dreg), (basereg), (disp)); \ } while(0) #define sse2_mulsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf2), (0x59), (dreg), (mem)); \ } while(0) #define sse_mulss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x59), (dreg), (reg)); \ } while(0) #define sse_mulss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0xf3), (0x59), (dreg), (basereg), (disp)); \ } while(0) #define sse_mulss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0xf3), (0x59), (dreg), (mem)); \ } while(0) #define sse3_mwait(inst) \ do { \ *(inst)++ = (unsigned char)0x0f; \ *(inst)++ = (unsigned char)0x01; \ *(inst)++ = (unsigned char)0xc9; \ } while(0) #define sse2_orpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x56), (dreg), (reg)); \ } while(0) #define sse2_orpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x56), (dreg), (basereg), (disp)); \ } while(0) #define sse2_orpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x56), (dreg), (mem)); \ } while(0) #define sse_orps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x56), (dreg), (reg)); \ } while(0) #define sse_orps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0x56), (dreg), (basereg), (disp)); \ } while(0) #define sse_orps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0x56), (dreg), (mem)); \ } while(0) #define sse2_packsswb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x63), (dreg), (reg)); \ } while(0) #define sse2_packsswb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x63), (dreg), (basereg), (disp)); \ } while(0) #define sse2_packsswb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x63), (dreg), (mem)); \ } while(0) #define sse2_packssdw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x6b), (dreg), (reg)); \ } while(0) #define sse2_packssdw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x6b), (dreg), (basereg), (disp)); \ } while(0) #define sse2_packssdw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x6b), (dreg), (mem)); \ } while(0) #define sse2_packuswb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x67), (dreg), (reg)); \ } while(0) #define sse2_packuswb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x67), (dreg), (basereg), (disp)); \ } while(0) #define sse2_packuswb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x67), (dreg), (mem)); \ } while(0) #define sse2_paddb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xfc), (dreg), (reg)); \ } while(0) #define sse2_paddb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xfc), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xfc), (dreg), (mem)); \ } while(0) #define sse2_paddw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xfd), (dreg), (reg)); \ } while(0) #define sse2_paddw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xfd), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xfd), (dreg), (mem)); \ } while(0) #define sse2_paddd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xfe), (dreg), (reg)); \ } while(0) #define sse2_paddd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xfe), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xfe), (dreg), (mem)); \ } while(0) #define sse2_paddq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xd4), (dreg), (reg)); \ } while(0) #define sse2_paddq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xd4), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xd4), (dreg), (mem)); \ } while(0) #define sse2_paddsb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xec), (dreg), (reg)); \ } while(0) #define sse2_paddsb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xec), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddsb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xec), (dreg), (mem)); \ } while(0) #define sse2_paddsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xed), (dreg), (reg)); \ } while(0) #define sse2_paddsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xed), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xed), (dreg), (mem)); \ } while(0) #define sse2_paddusb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xdc), (dreg), (reg)); \ } while(0) #define sse2_paddusb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xdc), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddusb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xdc), (dreg), (mem)); \ } while(0) #define sse2_paddusw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xdd), (dreg), (reg)); \ } while(0) #define sse2_paddusw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xdd), (dreg), (basereg), (disp)); \ } while(0) #define sse2_paddusw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xdd), (dreg), (mem)); \ } while(0) #define sse2_pand_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xdb), (dreg), (reg)); \ } while(0) #define sse2_pand_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xdb), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pand_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xdb), (dreg), (mem)); \ } while(0) #define sse2_pandn_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xdf), (dreg), (reg)); \ } while(0) #define sse2_pandn_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xdf), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pandn_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xdf), (dreg), (mem)); \ } while(0) #define sse_pavgb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe0), (dreg), (reg)); \ } while(0) #define sse_pavgb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe0), (dreg), (basereg), (disp)); \ } while(0) #define sse_pavgb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe0), (dreg), (mem)); \ } while(0) #define sse_pavgw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe3), (dreg), (reg)); \ } while(0) #define sse_pavgw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe3), (dreg), (basereg), (disp)); \ } while(0) #define sse_pavgw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe3), (dreg), (mem)); \ } while(0) #define sse2_pcmpeqb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x74), (dreg), (reg)); \ } while(0) #define sse2_pcmpeqb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x74), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpeqb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x74), (dreg), (mem)); \ } while(0) #define sse2_pcmpeqw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x75), (dreg), (reg)); \ } while(0) #define sse2_pcmpeqw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x75), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpeqd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x76), (dreg), (reg)); \ } while(0) #define sse2_pcmpeqd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x76), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpeqd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x76), (dreg), (mem)); \ } while(0) #define sse2_pcmpgtb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x64), (dreg), (reg)); \ } while(0) #define sse2_pcmpgtb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x64), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpgtb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x64), (dreg), (mem)); \ } while(0) #define sse2_pcmpgtw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x65), (dreg), (reg)); \ } while(0) #define sse2_pcmpgtw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x65), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpgtw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x65), (dreg), (mem)); \ } while(0) #define sse2_pcmpgtd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x66), (dreg), (reg)); \ } while(0) #define sse2_pcmpgtd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0x66), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pcmpgtd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0x66), (dreg), (mem)); \ } while(0) #define sse_pextrw_reg_mmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0xc5), (dreg), (reg)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define sse_pextrw_reg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xc5), (dreg), (reg)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define sse_pinsrw_xmreg_reg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xc4), (dreg), (reg)); \ *(inst)++ = (unsigned char)((int)(imm) & 0xff); \ } while(0) #define sse_pinsrw_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xc4), (dreg), (basereg),(disp)); \ *(inst)++ = (unsigned char)((int)(imm) & 0xff); \ } while(0) #define sse_pinsrw_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xc4), (dreg), (mem)); \ *(inst)++ = (unsigned char)((int)(imm) & 0xff); \ } while(0) #define sse2_pmaddwd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xf5), (dreg), (reg)); \ } while(0) #define sse2_pmaddwd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xf5), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pmaddwd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xf5), (dreg), (mem)); \ } while(0) #define sse_pmaxsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xee), (dreg), (reg)); \ } while(0) #define sse_pmaxsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xee), (dreg), (basereg), (disp)); \ } while(0) #define sse_pmaxsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xee), (dreg), (mem)); \ } while(0) #define sse_pmaxub_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xde), (dreg), (reg)); \ } while(0) #define sse_pmaxub_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xde), (dreg), (basereg), (disp)); \ } while(0) #define sse_pmaxub_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xde), (dreg), (mem)); \ } while(0) #define sse_pminsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xea), (dreg), (reg)); \ } while(0) #define sse_pminsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xea), (dreg), (basereg), (disp)); \ } while(0) #define sse_pminsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xea), (dreg), (mem)); \ } while(0) #define sse_pminub_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xda), (dreg), (reg)); \ } while(0) #define sse_pminub_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xda), (dreg), (basereg), (disp)); \ } while(0) #define sse_pminub_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xda), (dreg), (mem)); \ } while(0) #define sse_pmovmskb_reg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xd7), (dreg), (reg)); \ } while(0) #define sse_pmovmskb_reg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0xd7), (dreg), (reg)); \ } while(0) #define sse_pmulhuw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe4), (dreg), (reg)); \ } while(0) #define sse_pmulhuw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe4), (dreg), (basereg), (disp)); \ } while(0) #define sse_pmulhuw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe4), (dreg), (mem)); \ } while(0) #define sse2_pmulhw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe5), (dreg), (reg)); \ } while(0) #define sse2_pmulhw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe5), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pmulhw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe5), (dreg), (mem)); \ } while(0) #define sse2_pmullw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xd5), (dreg), (reg)); \ } while(0) #define sse2_pmullw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xd5), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pmullw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xd5), (dreg), (mem)); \ } while(0) #define sse2_pmuludq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xf4), (dreg), (reg)); \ } while(0) #define sse2_pmuludq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xf4), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pmuludq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xf4), (dreg), (mem)); \ } while(0) #define sse2_pmuludq_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0xf4), (dreg), (reg)); \ } while(0) #define sse2_pmuludq_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0xf4), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pmuludq_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0xf4), (dreg), (mem)); \ } while(0) #define sse2_por_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xfe), (dreg), (reg)); \ } while(0) #define sse2_por_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xfe), (dreg), (basereg), (disp)); \ } while(0) #define sse2_por_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xfe), (dreg), (mem)); \ } while(0) #define sse_psadbw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xf6), (dreg), (reg)); \ } while(0) #define sse_psadbw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xf6), (dreg), (basereg), (disp)); \ } while(0) #define sse_psadbw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xf6), (dreg), (mem)); \ } while(0) #define sse2_pshufd_xmreg_xmreg_imm8(inst,dreg,reg,mode) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshufd_xmreg_membase_imm8(inst,dreg,basereg,disp,mode) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg),(disp)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshufd_xmreg_mem_imm8(inst,dreg,mem,mode) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_mem((inst), (dreg), (basereg),(disp)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshufhwd_xmreg_xmreg_imm8(inst,dreg,reg,mode) \ do { \ *(inst) ++ = (unsigned char)0xf3; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshufhwd_xmreg_membase_imm8(inst,dreg,basereg,disp,mode) \ do { \ *(inst) ++ = (unsigned char)0xf3; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg),(disp)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshufhwd_xmreg_mem_imm8(inst,dreg,mem,mode) \ do { \ *(inst) ++ = (unsigned char)0xf3; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshuflw_xmreg_xmreg_imm8(inst,dreg,reg,mode) \ do { \ *(inst) ++ = (unsigned char)0xf2; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshuflw_xmreg_membase_imm8(inst,dreg,basereg,disp,mode) \ do { \ *(inst) ++ = (unsigned char)0xf2; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pshuflw_xmreg_mem_imm8(inst,dreg,mem,mode) \ do { \ *(inst) ++ = (unsigned char)0xf2; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x70; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_pslldq_xmreg_imm8(inst,dreg,mode) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_sse_operand_reg_reg((inst), (dreg), (XMM7)); \ *(inst) ++ = (unsigned char)((int)(mode) & 0xff); \ } while(0) #define sse2_psllw_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_sse_operand_reg_membase((inst), (dreg), (reg)); \ } while(0) #define sse2_psllw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psllw_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf1; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_psllw_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_sse_operand_reg_reg((inst), (XMM6), (dreg)); \ *(inst) ++ = (unsigned char)((int)(shift) & 0xff); \ } while(0) #define sse2_pslld_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse2_pslld_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg),(disp)); \ } while(0) #define sse2_pslld_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf2; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_pslld_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_sse_operand_reg_reg((inst), (XMM6), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psllq_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse2_psllq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psllq_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xf3; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_psllq_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_sse_operand_reg_reg((inst), (XMM6), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psraw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe1), (dreg), (reg)); \ } while(0) #define sse2_psraw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe1), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psraw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe1), (dreg), (mem)); \ } while(0) #define sse2_psraw_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_sse_operand_reg_reg((inst), (XMM4), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrad_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xe2), (dreg), (reg)); \ } while(0) #define sse2_psrad_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xe2), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psrad_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xe2), (dreg), (mem)); \ } while(0) #define sse2_psrad_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_sse_operand_reg_reg((inst), (XMM4), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psraw_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0xe1), (dreg), (reg)); \ } while(0) #define sse2_psraw_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0xe1), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psraw_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0xe1), (dreg), (mem)); \ } while(0) #define sse2_psraw_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_sse_operand_reg_reg((inst), (XMM4), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrad_mmreg_mmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0xe2), (dreg), (reg)); \ } while(0) #define sse2_psrad_mmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x0), (0xe2), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psrad_mmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x0), (0xe2), (dreg), (mem)); \ } while(0) #define sse2_psrad_mmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_sse_operand_reg_reg((inst), (XMM4), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrldq_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_sse_operand_reg_reg((inst), (XMM3), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrlw_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse2_psrlw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psrlw_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd1; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_psrlw_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x71; \ emit_sse_operand_reg_reg((inst), (XMM2), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrld_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse2_psrld_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psrld_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd2; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_psrld_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x72; \ emit_sse_operand_reg_reg((inst), (XMM2), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psrlq_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse2_psrlq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_sse_operand_reg_membase((inst), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psrlq_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xd3; \ emit_sse_operand_reg_mem((inst), (dreg), (mem)); \ } while(0) #define sse2_psrlq_xmreg_imm8(inst,dreg,shift) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x73; \ emit_sse_operand_reg_reg((inst), (XMM2), (dreg)); \ *(inst) ++ = (unsigned char)(int)((shift) & 0xff); \ } while(0) #define sse2_psubb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xf8), (dreg), (reg)); \ } while(0) #define sse2_psubb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xf8), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xf8), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xf9), (dreg), (reg)); \ } while(0) #define sse2_psubw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xf9), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xf9), (dreg), (mem)); \ } while(0) #define sse2_psubd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xfa), (dreg), (reg)); \ } while(0) #define sse2_psubd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xfa), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xfa), (dreg), (mem)); \ } while(0) #define sse2_psubq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0xfb), (dreg), (reg)); \ } while(0) #define sse2_psubq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase((inst), (0x66), (0xfb), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem((inst), (0x66), (0xfb), (dreg), (mem)); \ } while(0) #define sse2_psubsb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xe8), (dreg), (reg)); \ } while(0) #define sse2_psubsb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xe8), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubsb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xe8), (dreg), (mem)); \ } while(0) #define sse2_psubsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xe9), (dreg), (reg)); \ } while(0) #define sse2_psubsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xe9), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xe9), (dreg), (mem)); \ } while(0) #define sse2_psubusb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xd8), (dreg), (reg)); \ } while(0) #define sse2_psubusw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xd9), (dreg), (basereg), (disp)); \ } while(0) #define sse2_psubusw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xd9), (dreg), (mem)); \ } while(0) #define sse2_punpckhbw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x68), (dreg), (reg)); \ } while(0) #define sse2_punpckhbw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x68), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpckhbw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x68), (dreg), (mem)); \ } while(0) #define sse2_punpckhwd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x69), (dreg), (reg)); \ } while(0) #define sse2_punpckhwd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x69), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpckhwd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x69), (dreg), (mem)); \ } while(0) #define sse2_punpckhdq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x6a), (dreg), (reg)); \ } while(0) #define sse2_punpckhdq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x6a), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpckhdq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x6a), (dreg), (mem)); \ } while(0) #define sse2_punpckhqdq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x6d), (dreg), (reg)); \ } while(0) #define sse2_punpckhqdq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x6d), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpckhqdq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x6d), (dreg), (mem)); \ } while(0) #define sse2_punpcklbw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x60), (dreg), (reg)); \ } while(0) #define sse2_punpcklbw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x60), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpcklbw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x60), (dreg), (mem)); \ } while(0) #define sse2_punpcklwd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x61), (dreg), (reg)); \ } while(0) #define sse2_punpcklwd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x61), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpcklwd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x61), (dreg), (mem)); \ } while(0) #define sse2_punpckldq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x62), (dreg), (reg)); \ } while(0) #define sse2_punpckldq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x62), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpckldq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x62), (dreg), (mem)); \ } while(0) #define sse2_punpcklqdq_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x6C), (dreg), (reg)); \ } while(0) #define sse2_punpcklqdq_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x6C), (dreg), (basereg), (disp)); \ } while(0) #define sse2_punpcklqdq_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x6C), (dreg), (mem)); \ } while(0) #define sse2_pxor_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xef), (dreg), (reg)); \ } while(0) #define sse2_pxor_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xef), (dreg), (basereg), (disp)); \ } while(0) #define sse2_pxor_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xef), (dreg), (mem)); \ } while(0) #define sse_rcpps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x0), (0x53), (dreg), (reg)); \ } while(0) #define sse_rcpps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x53), (dreg), (basereg), (disp)); \ } while(0) #define sse_rcpps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x53), (dreg), (mem)); \ } while(0) #define sse_rcpss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0xf3), (0x53), (dreg), (reg)); \ } while(0) #define sse_rcpss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf3), (0x53), (dreg), (basereg), (disp)); \ } while(0) #define sse_rcpss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf3), (0x53), (dreg), (mem)); \ } while(0) #define sse_rsqrtps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x0), (0x52), (dreg), (reg)); \ } while(0) #define sse_rsqrtps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x52), (dreg), (basereg), (disp)); \ } while(0) #define sse_rsqrtps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x52), (dreg), (mem)); \ } while(0) #define sse_rsqrtss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0xf3), (0x52), (dreg), (reg)); \ } while(0) #define sse_rsqrtss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf3), (0x52), (dreg), (basereg), (disp)); \ } while(0) #define sse_rsqrtss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf3), (0x52), (dreg), (mem)); \ } while(0) #define sse2_shufpd_xmreg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0xc6), (dreg), (reg)); \ *(inst)++ = (unsigned char)imm; \ } while(0) #define sse2_shufpd_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0xc6), (dreg), (basereg), (disp)); \ *(inst) ++ = (unsigned char)(int)((imm) & 0xff); \ } while(0) #define sse2_shufpd_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0xc6), (dreg), (mem)); \ *(inst) ++ = (unsigned char)(int)((imm) & 0xff); \ } while(0) #define sse_shufps_xmreg_xmreg_imm8(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg(inst, (0x0), (0xc6), (dreg), (reg)); \ *(inst) ++ = (unsigned char)(int)((imm) & 0xff); \ } while(0) #define sse_shufps_xmreg_membase_imm8(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0xc6), (dreg), (basereg), (disp)); \ *(inst) ++ = (unsigned char)(int)((imm) & 0xff); \ } while(0) #define sse_shufps_xmreg_mem_imm8(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0xc6), (dreg), (mem); \ *(inst) ++ = (unsigned char)(int)((imm) & 0xff); \ } while(0) #define sse2_sqrtpd_xmreg_xmreg(inst,dreg,reg,imm) \ do { \ emit_sse_instruction_reg_reg(inst, (0x66), (0x51), (dreg), (reg)); \ } while(0) #define sse2_sqrtpd_xmreg_membase(inst,dreg,basereg,disp,imm) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x51), (dreg), (basereg), (disp)); \ } while(0) #define sse2_sqrtpd_xmreg_mem(inst,dreg,mem,imm) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x51), (dreg), (mem)); \ } while(0) #define sse_sqrtps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg(inst, (0x0), (0x51), (dreg), (reg)); \ } while(0) #define sse_sqrtps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x51), (dreg), (basereg), (disp)); \ } while(0) #define sse_sqrtps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x51), (dreg), (mem)); \ } while(0) #define sse2_sqrtsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x51), (dreg), (reg)); \ } while(0) #define sse2_sqrtsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf2), (0x51), (dreg), (basereg), (disp)); \ } while(0) #define sse2_sqrtsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf2), (0x51), (dreg), (mem)); \ } while(0) #define sse_sqrtss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x51), (dreg), (reg)); \ } while(0) #define sse_sqrtss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf3), (0x51), (dreg), (basereg), (disp)); \ } while(0) #define sse_sqrtss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf3), (0x51), (dreg), (mem)); \ } while(0) #define sse_stmxcsr_mem(inst,mem) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_mem((inst), (X86_EBX), (mem)); \ } while(0) #define sse_stmxcsr_membase(inst,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0xae; \ emit_sse_operand_reg_membase((inst), (X86_EBX), (basereg), (disp)); \ } while(0) #define sse_subpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x5c), (dreg), (reg)); \ } while(0) #define sse2_subpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x5c), (dreg), (basereg), (disp)); \ } while(0) #define sse2_subpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x5c), (dreg), (mem)); \ } while(0) #define sse_subps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x5c), (dreg), (reg)); \ } while(0) #define sse_subps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x5c), (dreg), (basereg), (disp)); \ } while(0) #define sse_subps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x5c), (dreg), (mem)); \ } while(0) #define sse2_subsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf2), (0x5c), (dreg), (reg)); \ } while(0) #define sse2_subsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf2), (0x5c), (dreg), (basereg), (disp)); \ } while(0) #define sse2_subsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf2), (0x5c), (dreg), (mem)); \ } while(0) #define sse_subss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0xf3), (0x5c), (dreg), (reg)); \ } while(0) #define sse_subss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0xf3), (0x5c), (dreg), (basereg), (disp)); \ } while(0) #define sse_subss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0xf3), (0x5c), (dreg), (mem)); \ } while(0) #define sse2_ucomisd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x2e), (dreg), (reg)); \ } while(0) #define sse2_ucomisd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x2e), (dreg), (basereg), (disp)); \ } while(0) #define sse2_ucomisd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x2e), (dreg), (mem)); \ } while(0) #define sse_ucomiss_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x2e), (dreg), (reg)); \ } while(0) #define sse_ucomiss_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x2e), (dreg), (basereg), (disp)); \ } while(0) #define sse_ucomiss_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x2e), (dreg), (mem)); \ } while(0) #define sse2_unpckhpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x15), (dreg), (reg)); \ } while(0) #define sse2_unpckhpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x15), (dreg), (basereg), (disp)); \ } while(0) #define sse2_unpckhpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x15), (dreg), (mem)); \ } while(0) #define sse_unpckhps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x15), (dreg), (reg)); \ } while(0) #define sse_unpckhps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x15), (dreg), (basereg), (disp)); \ } while(0) #define sse_unpckhps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x15), (dreg), (mem)); \ } while(0) #define sse2_unpcklpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x66), (0x14), (dreg), (reg)); \ } while(0) #define sse2_unpcklpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x14), (dreg), (basereg), (disp)); \ } while(0) #define sse2_unpcklpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x14), (dreg), (mem)); \ } while(0) #define sse_unpcklps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction_reg_reg((inst), (0x0), (0x14), (dreg), (reg)); \ } while(0) #define sse_unpcklps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x14), (dreg), (basereg), (disp)); \ } while(0) #define sse_unpcklps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x14), (dreg), (mem)); \ } while(0) #define sse2_xorpd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x66), (0x57), (dreg), (reg)); \ } while(0) #define sse2_xorpd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x66), (0x57), (dreg), (basereg), (disp)); \ } while(0) #define sse2_xorpd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x66), (0x57), (dreg), (mem)); \ } while(0) #define sse_xorps_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse_instruction((inst), (0x0), (0x57), (dreg), (reg)); \ } while(0) #define sse_xorps_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse_instruction_reg_membase(inst, (0x0), (0x57), (dreg), (basereg), (disp)); \ } while(0) #define sse_xorps_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse_instruction_reg_mem(inst, (0x0), (0x57), (dreg), (mem)); \ } while(0) #define sse4_pshufb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x0), (dreg), (reg)); \ } while(0) #define sse4_pshufb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x0), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pshufb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x0), (dreg), (mem)); \ } while(0) #define sse4_phaddw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x1), (dreg), (reg)); \ } while(0) #define sse4_phaddw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x1), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phaddw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x1), (dreg), (mem)); \ } while(0) #define sse4_phaddd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x2), (dreg), (reg)); \ } while(0) #define sse4_phaddd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x2), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phaddd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x2), (dreg), (mem)); \ } while(0) #define sse4_phaddsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x3), (dreg), (reg)); \ } while(0) #define sse4_phaddsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x3), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phaddsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x3), (dreg), (mem)); \ } while(0) #define sse4_pmaddubsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x4), (dreg), (reg)); \ } while(0) #define sse4_pmaddubsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x4), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pmaddubsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x4), (dreg), (mem)); \ } while(0) #define sse4_phsubsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x5), (dreg), (reg)); \ } while(0) #define sse4_phsubsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x5), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phsubsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x5), (dreg), (mem)); \ } while(0) #define sse4_phsubw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x6), (dreg), (reg)); \ } while(0) #define sse4_phsubw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x6), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phsubw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x6), (dreg), (mem)); \ } while(0) #define sse4_phsubd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x7), (dreg), (reg)); \ } while(0) #define sse4_phsubd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x7), (dreg), (basereg), (disp)); \ } while(0) #define sse4_phsubd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x7), (dreg), (mem)); \ } while(0) #define sse4_psignb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x8), (dreg), (reg)); \ } while(0) #define sse4_psignb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x8), (dreg), (basereg), (disp)); \ } while(0) #define sse4_psignb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x8), (dreg), (mem)); \ } while(0) #define sse4_psignw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x9), (dreg), (reg)); \ } while(0) #define sse4_psignw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x9), (dreg), (basereg), (disp)); \ } while(0) #define sse4_psignw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x9), (dreg), (mem)); \ } while(0) #define sse4_psignd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0xA), (dreg), (reg)); \ } while(0) #define sse4_psignd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0xA), (dreg), (basereg), (disp)); \ } while(0) #define sse4_psignd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0xA), (dreg), (mem)); \ } while(0) #define sse4_pmulhrsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0xB), (dreg), (reg)); \ } while(0) #define sse4_pmulhrsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0xB), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pmulhrsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0xB), (dreg), (mem)); \ } while(0) #define sse4_pabsb_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x1C), (dreg), (reg)); \ } while(0) #define sse4_pabsb_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x1C), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pabsb_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x1C), (dreg), (mem)); \ } while(0) #define sse4_pabsw_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x1D), (dreg), (reg)); \ } while(0) #define sse4_pabsw_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x1D), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pabsw_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x1D), (dreg), (mem)); \ } while(0) #define sse4_pabsd_xmreg_xmreg(inst,dreg,reg) \ do { \ emit_sse4_instruction_reg_reg(inst, (0x1E), (dreg), (reg)); \ } while(0) #define sse4_pabsd_xmreg_membase(inst,dreg,basereg,disp) \ do { \ emit_sse4_instruction_reg_membase(inst, (0x1E), (dreg), (basereg), (disp)); \ } while(0) #define sse4_pabsd_xmreg_mem(inst,dreg,mem) \ do { \ emit_sse4_instruction_reg_mem(inst, (0x1E), (dreg), (mem)); \ } while(0) #define sse4_palignr_xmreg_xmreg(inst,dreg,reg) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x3a; \ *(inst) ++ = (unsigned char)0x0f; \ emit_sse_operand_reg_reg((inst), (dreg), (reg)); \ } while(0) #define sse4_palignr_xmreg_membase(inst,dreg,basereg,disp) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x3a; \ *(inst) ++ = (unsigned char)0x0f; \ emit_sse_operand_reg_membase(inst, (dreg), (basereg), (disp)); \ } while(0) #define sse4_palignr_xmreg_mem(inst,dreg,mem) \ do { \ *(inst) ++ = (unsigned char)0x66; \ *(inst) ++ = (unsigned char)0x0f; \ *(inst) ++ = (unsigned char)0x3a; \ *(inst) ++ = (unsigned char)0x0f; \ emit_sse_operand_reg_mem(inst, (dreg), (mem)); \ } while(0) #endif /* JIT_GEN_SSE_H */