I reworked the header for ATmega640/1280/2560/641/1281/2561 so that when a 64pin device is use, missing pin definition are not declared. It use the same mechanism that was already in place in that file.

This patch also fix issue where USART Rx 0 and XCLK where missing the '0'.

This patch against HEAD and not against the previously committed patch.

(file #18037)

Hi,

Latest patch against HEAD,
Solve:
- Duplicate issue
- Now Output Compare that are Inverted are named OCXY_N:
#define OC1D_N_DDR  DDRB
#define OC1D_N_PORT PORTB
#define OC1D_N_PIN  PINB
#define OC1D_N_BIT  4

Comments are welcome.

(file #17941)

I'm including 2 files:
io.patch
xml.patch

added pin definition
added an INTERRUPT_num

TODO:
Some device have no pin definition since XML files lack information.
Some device like ATmega1280/1281 use the same io file, however the 1281 has less pin, should consider using the already existing _ATmegaxx1_ and _ATmegaxx0_ define
Some device may contain errors since the XML are crappy


(file #17813, file #17814)

It's a common thing when single pin on a device represents several features, for example atmega8:
PORTB:
  PB5 can be used as regular i/o port or SCK for SPI interface
  PB4 can be used as regular i/o port or MISO for SPI interface
  PB3 can be used as regular i/o port or MOSI for SPI interface
  PB2 can be used as regular i/o port or SS for SPI interface
PORTD:
  PD0 can be used as regular i/o port or RX for usart
  PD1 can be used as regular i/o port or TX for usart
etc...
Almost every pin have several meanings. So if I'm trying to build software wich communicates using for example SPI interface, i have to use some of i/o ports in another meaning(write logical 1/0 to SS pin to select/deselect slave device) So i think it's a good idea to put such definitions to headers:

for example:
#define SS   PB2
#define MOSI PB3
#define MISO PB4
#define SCK  PB5
#define SPI_PORT PORTB


#define RX PD0
#define TX PD1
#define USART_PORT PORTD