Wed 07 Dec 2011 02:29:44 PM UTC, original submission:
While debugging my code I found a bug/race condition in avr/wdt.h that left me astonished (since that code is in effect for a long time now).
Assembly code (ATtiny, ATmega, AT90 parts) for the inline wdt_enable() possibly re-enables interrupts before the last write access to WDTCSR.
The bug is present both for STS/OUT instructions code.
Note in fact how for STS code we have
the OUT to SREG happens right before the last STS to WDTCSR, making the code non-atomic: the last STS to WDTCSR could be delayed (by an interrupt handler) for many cycles, voiding its effect (has to happen within 4 cycles from the precedent STS to WDTCSR).
The same happens for OUT instruction mode in wdt_enable(), while wdt_disable() is always correct (OUT to SREG is last instruction).
For ATxmega parts code in wdt_enable() is correct, but I can't see a wdt_disable() defined anywhere: am I right? Is that intentional?
~Lou
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