bugSimulavr: an AVR simulator - Bugs: bug #35195, ICALL simulation: wrong cycles

 
 

bug #35195: ICALL simulation: wrong cycles

Submitted by:  None
Submitted on:  Fri 30 Dec 2011 09:12:24 AM UTC  
 
Category: SimulationSeverity: 3 - Normal
Item Group: NoneStatus: Fixed
Privacy: PublicAssigned to: None
Originator Email: -unavailable-Open/Closed: Closed
Component Version: simulavr

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Wed 04 Jan 2012 08:50:31 PM UTC, comment #2:

Fix committed. Thanks for the patch.
http://git.savannah.gnu.org/cgit/simulavr.git/commit/?id=ae8b9a718b07514acda7fe6368b1e08302eaaf52

Petr Hluzin <petrh>
Project Member
Wed 04 Jan 2012 04:28:44 PM UTC, comment #1:

Hi Erich,

just to keep you uptodate. I posted a patch to this bug on the mailing list, which was not yet committed. If you want to try it out by yourself, please have a look at http://lists.nongnu.org/archive/html/simulavr-devel/2011-12/msg00018.html

Bye, Stan.

Anonymous
Fri 30 Dec 2011 09:12:24 AM UTC, original submission:

Hi,

working simulavr: git clone (one month ago)
processor: atmega128

ICALL should take 3 cycles to execute, but the simulator finishes its execution within one cycle.

(I need the cycle accuracy for a cycle accurate atmega128 written in VHDL)

./c_code/main.elf 0x02e8: test_assembler+0x108 {LDI R30, 0x00 }
./c_code/main.elf 0x02ea: test_assembler+0x109 {LDI R31, 0x01 }
./c_code/main.elf 0x02ec: test_assembler+0x10a {ICALL Z SP=0x10fa 0x77 SP=0x10f9 0x1 }
./c_code/main.elf 0x0200: test_assembler+0x94 {FMULS R18, R19 SREG=[--H---Z-] }

Best regards,
Erich

Anonymous

 

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    Follow 2 latest changes.

    Date Changed By Updated Field Previous Value => Replaced By
    Wed 04 Jan 2012 08:50:31 PM UTCpetrhStatusNone=>Fixed
      Open/ClosedOpen=>Closed

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