µracoli Manual
Version foo
µracoli
User Guide
Reference Guide
at86rf212.h
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/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf212.txt */
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/* Copyright (c) 2008 Axel Wachtler
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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* Neither the name of the authors nor the names of its contributors
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may be used to endorse or promote products derived from this software
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without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* $Id$ */
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#ifndef AT86RF212_H
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#define AT86RF212_H (1)
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/* === Includes ============================================================== */
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/* === Externals ============================================================= */
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/* === Types ================================================================= */
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typedef
uint8_t
trx_ramaddr_t
;
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typedef
uint8_t
trx_regval_t
;
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typedef
uint8_t
trx_regaddr_t
;
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/* === Macros ================================================================ */
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#define RG_TRX_STATUS (0x1)
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#define SR_CCA_DONE 0x1,0x80,7
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#define SR_CCA_STATUS 0x1,0x40,6
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#define SR_TRX_STATUS 0x1,0x1f,0
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#ifndef P_ON
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#define P_ON (0)
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#endif
/* P_ON */
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#ifndef BUSY_RX
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#define BUSY_RX (1)
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#endif
/* BUSY_RX */
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#ifndef BUSY_TX
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#define BUSY_TX (2)
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#endif
/* BUSY_TX */
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#ifndef RX_ON
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#define RX_ON (6)
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#endif
/* RX_ON */
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#ifndef TRX_OFF
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#define TRX_OFF (8)
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#endif
/* TRX_OFF */
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#ifndef PLL_ON
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#define PLL_ON (9)
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#endif
/* PLL_ON */
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#ifndef TRX_SLEEP
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#define TRX_SLEEP (15)
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#endif
/* TRX_SLEEP */
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#ifndef BUSY_RX_AACK
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#define BUSY_RX_AACK (17)
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#endif
/* BUSY_RX_AACK */
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#ifndef BUSY_TX_ARET
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#define BUSY_TX_ARET (18)
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#endif
/* BUSY_TX_ARET */
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#ifndef RX_AACK_ON
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#define RX_AACK_ON (22)
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#endif
/* RX_AACK_ON */
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#ifndef TX_ARET_ON
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#define TX_ARET_ON (25)
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#endif
/* TX_ARET_ON */
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#ifndef RX_ON_NOCLK
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#define RX_ON_NOCLK (28)
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#endif
/* RX_ON_NOCLK */
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#ifndef RX_AACK_ON_NOCLK
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#define RX_AACK_ON_NOCLK (29)
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#endif
/* RX_AACK_ON_NOCLK */
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#ifndef BUSY_RX_AACK_NOCLK
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#define BUSY_RX_AACK_NOCLK (30)
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#endif
/* BUSY_RX_AACK_NOCLK */
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#define RG_TRX_STATE (0x2)
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#define SR_TRAC_STATUS 0x2,0xe0,5
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#ifndef TRAC_SUCCESS
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#define TRAC_SUCCESS (0)
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#endif
/* TRAC_SUCCESS */
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#ifndef TRAC_SUCCESS_DATA_PENDING
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#define TRAC_SUCCESS_DATA_PENDING (1)
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#endif
/* TRAC_SUCCESS_DATA_PENDING */
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#ifndef TRAC_SUCCESS_WAIT_FOR_ACK
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#define TRAC_SUCCESS_WAIT_FOR_ACK (2)
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#endif
/* TRAC_SUCCESS_WAIT_FOR_ACK */
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#ifndef TRAC_CHANNEL_ACCESS_FAILURE
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#define TRAC_CHANNEL_ACCESS_FAILURE (3)
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#endif
/* TRAC_CHANNEL_ACCESS_FAILURE */
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#ifndef TRAC_NO_ACK
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#define TRAC_NO_ACK (5)
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#endif
/* TRAC_NO_ACK */
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#ifndef TRAC_INVALID
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#define TRAC_INVALID (7)
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#endif
/* TRAC_INVALID */
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#define SR_TRX_CMD 0x2,0x1f,0
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#ifndef CMD_NOP
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#define CMD_NOP (0)
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#endif
/* CMD_NOP */
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#ifndef CMD_TX_START
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#define CMD_TX_START (2)
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#endif
/* CMD_TX_START */
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#ifndef CMD_FORCE_TRX_OFF
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#define CMD_FORCE_TRX_OFF (3)
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#endif
/* CMD_FORCE_TRX_OFF */
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#ifndef CMD_RX_ON
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#define CMD_RX_ON (6)
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#endif
/* CMD_RX_ON */
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#ifndef CMD_TRX_OFF
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#define CMD_TRX_OFF (8)
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#endif
/* CMD_TRX_OFF */
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#ifndef CMD_PLL_ON
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#define CMD_PLL_ON (9)
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#endif
/* CMD_PLL_ON */
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#ifndef CMD_RX_AACK_ON
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#define CMD_RX_AACK_ON (22)
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#endif
/* CMD_RX_AACK_ON */
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#ifndef CMD_TX_ARET_ON
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#define CMD_TX_ARET_ON (25)
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#endif
/* CMD_TX_ARET_ON */
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#define RG_TRX_CTRL_0 (0x3)
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#define SR_PAD_IO 0x3,0xc0,6
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#define SR_PAD_IO_CLKM 0x3,0x30,4
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#ifndef CLKM_2mA
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#define CLKM_2mA (0)
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#endif
/* CLKM_2mA */
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#ifndef CLKM_4mA
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#define CLKM_4mA (1)
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#endif
/* CLKM_4mA */
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#ifndef CLKM_6mA
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#define CLKM_6mA (2)
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#endif
/* CLKM_6mA */
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#ifndef CLKM_8mA
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#define CLKM_8mA (3)
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#endif
/* CLKM_8mA */
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#define SR_CLKM_SHA_SEL 0x3,0x8,3
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#define SR_CLKM_CTRL 0x3,0x7,0
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#ifndef CLKM_no_clock
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#define CLKM_no_clock (0)
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#endif
/* CLKM_no_clock */
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#ifndef CLKM_1MHz
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#define CLKM_1MHz (1)
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#endif
/* CLKM_1MHz */
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#ifndef CLKM_2MHz
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#define CLKM_2MHz (2)
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#endif
/* CLKM_2MHz */
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#ifndef CLKM_4MHz
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#define CLKM_4MHz (3)
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#endif
/* CLKM_4MHz */
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#ifndef CLKM_8MHz
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#define CLKM_8MHz (4)
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#endif
/* CLKM_8MHz */
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#ifndef CLKM_16MHz
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#define CLKM_16MHz (5)
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#endif
/* CLKM_16MHz */
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#define RG_TRX_CTRL_1 (0x4)
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#define SR_PA_EXT_EN 0x4,0x80,7
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#define SR_IRQ_2_EXT_EN 0x4,0x40,6
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#define SR_TX_AUTO_CRC_ON 0x4,0x20,5
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#define SR_RX_BL_CTRL 0x4,0x10,4
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#define SR_SPI_CMD_MODE 0x4,0xc,2
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#define SR_IRQ_POLARITY 0x4,0x1,0
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#define SR_IRQ_MASK_MODE 0x4,0x2,1
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#define RG_PHY_TX_PWR (0x5)
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#define SR_PA_BOOST 0x5,0x80,7
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#define SR_GC_PA 0x5,0x60,5
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#define SR_TX_PWR 0x5,0x1f,0
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#define RG_PHY_RSSI (0x6)
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#define SR_RX_CRC_VALID 0x6,0x80,7
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#define SR_RND_VALUE 0x6,0x60,5
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#define SR_RSSI 0x6,0x1f,0
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#define RG_PHY_ED_LEVEL (0x7)
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#define SR_ED_LEVEL 0x7,0xff,0
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#define RG_PHY_CC_CCA (0x8)
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#define SR_CCA_REQUEST 0x8,0x80,7
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#define SR_CCA_MODE 0x8,0x60,5
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#define SR_CHANNEL 0x8,0x1f,0
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#define RG_CCA_THRES (0x9)
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#define SR_CCA_ED_THRES 0x9,0xf,0
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#define RG_SFD_VALUE (0xb)
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#define SR_SFD_VALUE 0xb,0xff,0
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#define RG_TRX_CTRL_2 (0xc)
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#define SR_RX_SAFE_MODE 0xc,0x80,7
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#define SR_TRX_OFF_AVDD_EN 0xc,0x40,6
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#define SR_BPSK_OQPSK 0xc,0x8,3
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#define SR_SUB_MODE 0xc,0x4,2
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#define SR_OQPSK_DATA_RATE 0xc,0x3,0
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#define RG_ANT_DIV (0xd)
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#define SR_ANT_SEL 0xd,0x80,7
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#define SR_ANT_EXT_SW_EN 0xd,0x4,2
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#define SR_ANT_CTRL 0xd,0x3,0
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#define RG_IRQ_MASK (0xe)
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#define SR_MASK_BAT_LOW 0xe,0x80,7
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#define SR_MASK_TRX_UR 0xe,0x40,6
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#define SR_MASK_AMI 0xe,0x20,5
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#define SR_MASK_CCA_ED_READY 0xe,0x10,4
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#define SR_MASK_TRX_END 0xe,0x8,3
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#define SR_MASK_RX_START 0xe,0x4,2
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#define SR_MASK_PLL_LOCK 0xe,0x1,0
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#define SR_MASK_PLL_UNLOCK 0xe,0x2,1
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#define RG_IRQ_STATUS (0xf)
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#define SR_BAT_LOW 0xf,0x80,7
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#define SR_TRX_UR 0xf,0x40,6
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#define SR_AMI 0xf,0x20,5
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#define SR_CCA_ED_READY 0xf,0x10,4
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#define SR_TRX_END 0xf,0x8,3
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#define SR_RX_START 0xf,0x4,2
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#define SR_PLL_LOCK 0xf,0x1,0
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#define SR_PLL_UNLOCK 0xf,0x2,1
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#define RG_VREG_CTRL (0x10)
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#define SR_AVREG_EXT 0x10,0x80,7
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#define SR_AVDD_OK 0x10,0x40,6
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#define SR_DVREG_EXT 0x10,0x8,3
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#define SR_DVDD_OK 0x10,0x4,2
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#define RG_BATMON (0x11)
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#define SR_BATMON_OK 0x11,0x20,5
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#define SR_BATMON_HR 0x11,0x10,4
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#define SR_BATMON_VTH 0x11,0xf,0
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#define RG_XOSC_CTRL (0x12)
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#define SR_XTAL_MODE 0x12,0xf0,4
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#define SR_XTAL_TRIM 0x12,0xf,0
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#define RG_CC_CTRL_0 (0x13)
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#define SR_CC_NUMBER 0x13,0xff,0
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#define RG_CC_CTRL_1 (0x14)
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#define SR_CC_BAND 0x14,0x4,2
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#define SR_BAND 0x14,0x1,0
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#define SR_CC_ 0x14,0x2,1
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#define RG_RX_SYN (0x15)
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#define SR_RX_PDT_DIS 0x15,0x80,7
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#define SR_RX_PDT_LEVEL 0x15,0xf,0
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#define RG_RF_CTRL_0 (0x16)
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#define SR_PA_LT 0x16,0xc0,6
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#define SR_GC_TX_OFFS 0x16,0x3,0
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#define RG_XAH_CTRL_1 (0x17)
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#define SR_CSMA_LBT_MODE 0x17,0x80,7
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#define SR_AACK_FLTR_RES_FT 0x17,0x20,5
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#define SR_AACK_UPLD_RES_FT 0x17,0x10,4
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#define SR_AACK_ACK_TIME 0x17,0x4,2
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#define SR_AACK_PROM_MODE 0x17,0x2,1
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#define RG_FTN_CTRL (0x18)
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#define SR_FTN_START 0x18,0x80,7
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#define RG_RF_CTRL_1 (0x19)
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#define SR_RF_MC 0x19,0xf0,4
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#define RG_PLL_CF (0x1a)
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#define SR_PLL_CF_START 0x1a,0x80,7
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#define RG_PLL_DCU (0x1b)
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#define SR_PLL_DCU_START 0x1b,0x80,7
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#define RG_PART_NUM (0x1c)
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#define SR_PART_NUM 0x1c,0xff,0
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#ifndef RF212A_PART_NUM
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#define RF212A_PART_NUM (7)
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#endif
/* RF212A_PART_NUM */
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#define RG_VERSION_NUM (0x1d)
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#define SR_VERSION_NUM 0x1d,0xff,0
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#ifndef RF212A_VERSION_NUM
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#define RF212A_VERSION_NUM (1)
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#endif
/* RF212A_VERSION_NUM */
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#define RG_MAN_ID_0 (0x1e)
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#define SR_MAN_ID_0 0x1e,0xff,0
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#define RG_MAN_ID_1 (0x1f)
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#define SR_MAN_ID_1 0x1f,0xff,0
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#define RG_SHORT_ADDR_0 (0x20)
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#define SR_SHORT_ADDR_0 0x20,0xff,0
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#define RG_SHORT_ADDR_1 (0x21)
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#define SR_SHORT_ADDR_1 0x21,0xff,0
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#define RG_PAN_ID_0 (0x22)
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#define SR_PAN_ID_0 0x22,0xff,0
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#define RG_PAN_ID_1 (0x23)
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#define SR_PAN_ID_1 0x23,0xff,0
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#define RG_IEEE_ADDR_0 (0x24)
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#define SR_IEEE_ADDR_0 0x24,0xff,0
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#define RG_IEEE_ADDR_1 (0x25)
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#define SR_IEEE_ADDR_1 0x25,0xff,0
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#define RG_IEEE_ADDR_2 (0x26)
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#define SR_IEEE_ADDR_2 0x26,0xff,0
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#define RG_IEEE_ADDR_3 (0x27)
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#define SR_IEEE_ADDR_3 0x27,0xff,0
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#define RG_IEEE_ADDR_4 (0x28)
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#define SR_IEEE_ADDR_4 0x28,0xff,0
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#define RG_IEEE_ADDR_5 (0x29)
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#define SR_IEEE_ADDR_5 0x29,0xff,0
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#define RG_IEEE_ADDR_6 (0x2a)
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#define SR_IEEE_ADDR_6 0x2a,0xff,0
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#define RG_IEEE_ADDR_7 (0x2b)
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#define SR_IEEE_ADDR_7 0x2b,0xff,0
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#define RG_XAH_CTRL_0 (0x2c)
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#define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
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#define SR_SLOTTED_OPERATION 0x2c,0x1,0
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#define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
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#define RG_CSMA_SEED_0 (0x2d)
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#define SR_CSMA_SEED_0 0x2d,0xff,0
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#define RG_CSMA_SEED_1 (0x2e)
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#define SR_AACK_FVN_MODE 0x2e,0xc0,6
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#define SR_AACK_SET_PD 0x2e,0x20,5
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#define SR_AACK_DIS_ACK 0x2e,0x10,4
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#define SR_AACK_I_AM_COORD 0x2e,0x8,3
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#define SR_CSMA_SEED_1 0x2e,0x7,0
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#define RG_CSMA_BE (0x2f)
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#define SR_MAX_BE 0x2f,0xf0,4
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#define SR_MIN_BE 0x2f,0xf,0
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#define RADIO_NAME "AT86RF212"
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#define RADIO_PART_NUM (RF212A_PART_NUM)
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#define RADIO_VERSION_NUM (RF212A_VERSION_NUM)
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#define TRX_CMD_RW (_BV(7) | _BV(6))
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#define TRX_CMD_RR (_BV(7))
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#define TRX_CMD_FW (_BV(6) | _BV(5))
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#define TRX_CMD_FR (_BV(5))
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#define TRX_CMD_SW (_BV(6))
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#define TRX_CMD_SR (0)
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#define TRX_CMD_RADDR_MASK (0x3f)
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#define TRX_RESET_TIME_US (6)
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#define TRX_INIT_TIME_US (510)
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500
#define TRX_PLL_LOCK_TIME_US (180)
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502
504
#define TRX_CCA_TIME_US (140)
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#define TRX_IRQ_PLL_LOCK _BV(0)
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510
#define TRX_IRQ_PLL_UNLOCK _BV(1)
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#define TRX_IRQ_RX_START _BV(2)
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#define TRX_IRQ_TRX_END _BV(3)
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#define TRX_IRQ_CCA_ED _BV(4)
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#define TRX_IRQ_AMI _BV(5)
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#define TRX_IRQ_UR _BV(6)
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#define TRX_IRQ_BAT_LOW _BV(7)
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#define TRAC_SUCCESS (0)
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#define TRAC_CHANNEL_ACCESS_FAILURE (3)
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#define TRAC_NO_ACK (5)
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#define TRX_MIN_CHANNEL (0)
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#define TRX_MAX_CHANNEL (10)
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#define TRX_NB_CHANNELS (11)
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#define TRX_SUPPORTED_CHANNELS (0x00007ffUL)
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#define TRX_SUPPORTED_PAGES (42)
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#define TRX_SUPPORTS_BAND_700 (1)
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#define TRX_SUPPORTS_BAND_800 (1)
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#define TRX_SUPPORTS_BAND_900 (1)
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#define TRX_BPSK20 (0)
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#define TRX_BPSK40 (4)
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#define TRX_OQPSK100 (8)
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#define TRX_OQPSK200 (9)
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#define TRX_OQPSK400 (10)
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#define TRX_OQPSK400_1 (11)
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#define TRX_OQPSK250 (12)
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#define TRX_OQPSK500 (13)
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#define TRX_OQPSK1000 (14)
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#define TRX_OQPSK1000_1 (15)
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#define TRX_NONE (255)
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#endif
/* ifndef AT86RF212_H */
trx_regaddr_t
uint8_t trx_regaddr_t
Definition:
transceiver.h:89
trx_regval_t
uint8_t trx_regval_t
Definition:
transceiver.h:85
trx_ramaddr_t
uint8_t trx_ramaddr_t
Definition:
transceiver.h:81
install
inc
at86rf212.h
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