bugAVR C Runtime Library - Bugs: bug #26734, Unsafe SP register changes in...

 
 

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bug #26734: Unsafe SP register changes in ISR_NOBLOCK interrupt handlers

Submitter:  Anatoly Sokolov <aesok>
Submitted:  Wed 03 Jun 2009 02:10:16 AM UTC
   
 
Category:  Library Severity:  5 - Blocker
Priority:  9 - Immediate Item Group:  Header files
Status:  None Assigned to:  None
Percent Complete:  0% Open/Closed:  Open
Release:  1.6.6 Fixed Release:  None

Fri 08 Jun 2012 10:45:18 PM UTC, comment #2: 

With avr-gcc 4.7.1 and higher, attribute interrupt will override attribute signal, see

http://gcc.gnu.org/PR53256

and the GCC manual.

Georg-Johann Lay <gjlayde>
Wed 03 Jun 2009 03:07:00 AM UTC, comment #1: 

The ISR(INT0_vect,ISR_NOBLOCK) macro expand in:
void _vector_1 (void) __attribute_ ((signal,used, externally_visible)) _attribute_((interrupt)); void __vector_1 (void)

This code confused the GCC. The 'interrupt' attribute makes emit the 'sei' instruction but the 'signal' attribute makes don't disable interrupt when SP reg is changed.

This is bad use 'interrupt' and 'signal' attribute simultaneously.

1. I will add in the GCC code for checking incorrect attributes use. i.e use 'interrupt' and 'signal' attribute simultaneously for one function.

2. avr-libc should be modified and don't use 'interrupt' and 'signal' attribute simultaneously.

Anatoly.

Anatoly Sokolov <aesok>
Group administrator
Wed 03 Jun 2009 02:10:16 AM UTC, original submission:  

Test case:
#include <avr/interrupt.h>
#include <compat/deprecated.h>

ISR(INT0_vect,ISR_NOBLOCK)
{
  volatile long long foo;
 
  foo = 1;
}

INTERRUPT(PCINT0_vect)
{
  volatile long long foo;
 
  foo = 1;
}

int main(void)
{
  return 0;
}

For 'PCINT0_vect' interrupt handler correct code is generated:

INTERRUPT(PCINT0_vect)
{
  8c: 78 94       sei     // enable interrupt
....
  //  Correct. interrupt is disabled/enabled when SP register is changed
  9e: cd b7       in r28, 0x3d ; 61
  a0: de b7       in r29, 0x3e ; 62
  a2: 28 97       sbiw r28, 0x08 ; 8
  a4: f8 94       cli
  a6: de bf       out 0x3e, r29 ; 62
  a8: 78 94       sei
  aa: cd bf       out 0x3d, r28 ; 61

For 'INT0_vect' interrupt handler wrong code is generated:

ISR(INT0_vect,ISR_NOBLOCK)
{
  48: 78 94       sei     // enable interrupt
....
  //  WRONG! NO interrupt is disabled/enabled when SP register is changed
  5a: cd b7       in r28, 0x3d ; 61
  5c: de b7       in r29, 0x3e ; 62
  5e: 28 97       sbiw r28, 0x08 ; 8
  60: de bf       out 0x3e, r29 ; 62
  62: cd bf       out 0x3d, r28 ; 61

Anatoly.

Anatoly Sokolov <aesok>
Group administrator

 

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  • -email is unavailable- added by arcanum (Updated the item)
  • -email is unavailable- added by gjlayde (Posted a comment)
  • -email is unavailable- added by aesok (Submitted the item)
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    Follows 1 latest change.

    Date Changed by Updated Field Previous Value => Replaced by
    2012-11-16 arcanum Priority5 - Normal 9 - Immediate

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